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    SEMICONDUCTOR DEVICE INCLUDING DUMMY GATE PART AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DUMMY GATE PART AND METHOD OF FABRICATING THE SAME 审中-公开
    包括双门部分的半导体器件及其制造方法

    公开(公告)号：US20120028435A1

    公开(公告)日：2012-02-02

    申请号：US13240475

    申请日：2011-09-22

    申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    IPC分类号： H01L21/76

    CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

    摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

    摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

    Semiconductor device including dummy gate part and method of fabricating the same
    3.
    发明授权
    Semiconductor device including dummy gate part and method of fabricating the same 有权
    半导体器件包括伪栅极部分及其制造方法

    公开(公告)号：US08053845B2

    公开(公告)日：2011-11-08

    申请号：US12291211

    申请日：2008-11-07

    申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    IPC分类号： H01L21/70

    CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

    摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

    摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

    METHOD OF ADJUSTING PATTERN DENSITY
    4.
    发明申请
    METHOD OF ADJUSTING PATTERN DENSITY 审中-公开
    调整图案密度的方法

    公开(公告)号：US20070174802A1

    公开(公告)日：2007-07-26

    申请号：US11625569

    申请日：2007-01-22

    申请人： Jae-Pil SHIN ,  Moon-Hyun Yoo ,  Jong-Bae Lee ,  Jin-Sook Choi ,  Sung Gyu Park

    发明人： Jae-Pil SHIN ,  Moon-Hyun Yoo ,  Jong-Bae Lee ,  Jin-Sook Choi ,  Sung Gyu Park

    IPC分类号： G06F17/50

    CPC分类号： G03F1/80 ,  G03F1/36

    摘要： A method of adjusting pattern density includes determining a reference pattern density, defining dummy generation fields and designed patterns, forming basic dummy patterns on the dummy generation fields, evaluating a total pattern density from a sum of a density of the designed patterns and a density of the basic dummy patterns, adjusting a size of the basic dummy patterns so that the total pattern density reaches the reference pattern density, and combining data of the adjusted dummy patterns with data of the designed patterns.

    摘要翻译： 调整图案密度的方法包括确定参考图案密度，定义虚拟生成区域和设计图案，在虚拟生成区域上形成基本虚拟图案，从设计图案的密度和密度之和评估总图案密度 基本虚拟图案，调整基本虚拟图案的尺寸，使得总图案密度达到参考图案密度，以及将调整的图案数据与设计图案的数据组合。

    MASK SET FOR MICROARRAY, METHOD OF FABRICATING MASK SET, AND METHOD OF FABRICATING MICROARRAY USING MASK SET
    7.
    发明申请
    MASK SET FOR MICROARRAY, METHOD OF FABRICATING MASK SET, AND METHOD OF FABRICATING MICROARRAY USING MASK SET 审中-公开
    用于微阵列的掩模设置，制作掩模组的方法以及使用掩模设置微阵列的方法

    公开(公告)号：US20080193863A1

    公开(公告)日：2008-08-14

    申请号：US12030647

    申请日：2008-02-13

    申请人： Jae-pil Shin ,  Jin-sook Choi ,  Jung-hwan Hah ,  Moon-hyun Yoo ,  Jong-bae Lee

    发明人： Jae-pil Shin ,  Jin-sook Choi ,  Jung-hwan Hah ,  Moon-hyun Yoo ,  Jong-bae Lee

    IPC分类号： G03F7/00 ,  G03F1/00

    CPC分类号： G03F1/36 ,  G03F1/00

    摘要： Provided are a mask set for in-situ synthesizing probes of a microarray, a method of fabricating the mask set, and a method of fabricating the microarray using the mask set. A mask set for a microarray includes a plurality of masks for in-situ synthesizing probes onto a substrate which includes an array of a plurality of probe cells, wherein each mask includes light-transmitting regions and light-blocking regions, each probe cell corresponds to a light-transmitting region or a light-blocking region, and a pattern of each light-transmitting region is corrected for an optical proximity effect.

    摘要翻译： 提供了用于原位合成微阵列探针的掩模组，制造掩模组的方法，以及使用掩模组制造微阵列的方法。 用于微阵列的掩模组包括多个掩模，用于在包括多个探针单元的阵列的基板上原位合成探针，其中每个掩模包括透光区域和遮光区域，每个探针单元对应于 光透射区域或遮光区域以及每个透光区域的图案被校正为光学邻近效应。

    Semiconductor device including dummy gate part and method of fabricating the same
    8.
    发明申请
    Semiconductor device including dummy gate part and method of fabricating the same 有权
    半导体器件包括伪栅极部分及其制造方法

    公开(公告)号：US20090121296A1

    公开(公告)日：2009-05-14

    申请号：US12291211

    申请日：2008-11-07

    申请人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    发明人： Byoung-ho Kwon ,  Sang-youn Jo ,  Jin-sook Choi ,  Chang-ki Hong ,  Bo-un Yoon ,  Hong-soo Kim ,  Se-rah Yun

    IPC分类号： H01L27/10

    CPC分类号： H01L21/31053 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/66545

    摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

    摘要翻译： 在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。 半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。