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40 条记录 (耗时 0.021 秒)

    Leakage Reduction in Memory Devices
    1.
    发明申请
    Leakage Reduction in Memory Devices 有权
    内存设备中的泄漏减少

    公开(公告)号：US20100226191A1

    公开(公告)日：2010-09-09

    申请号：US12397142

    申请日：2009-03-03

    申请人： Changho Jung ,  Nan Chen ,  Cheng Zhong ,  Zhiqin Chen

    发明人： Changho Jung ,  Nan Chen ,  Cheng Zhong ,  Zhiqin Chen

    IPC分类号： G11C7/00 ,  G11C5/14

    CPC分类号： G11C7/00 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4094 ,  G11C11/413 ,  G11C2207/2227 ,  H03K19/0016

    摘要： A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches are added for pre-charge devices to further reduce leakage current.

    摘要翻译： 存储器件包括包括存储器单元的核心阵列。 存储器件还包括耦合到芯阵列的头灯和正电源电压。 磁头开关通过将磁芯阵列与正电源电压断开来减少来自磁芯阵列的漏电流。 另外，增加头开关用于预充电器件，以进一步减少泄漏电流。

    System and method of conditional control of latch circuit devices
    3.
    发明授权
    System and method of conditional control of latch circuit devices 有权
    锁存电路器件的条件控制系统及方法

    公开(公告)号：US07962681B2

    公开(公告)日：2011-06-14

    申请号：US11971353

    申请日：2008-01-09

    申请人： Hari Rao ,  Cheng Zhong ,  Zhiqin Chen

    发明人： Hari Rao ,  Cheng Zhong ,  Zhiqin Chen

    IPC分类号： G06F13/00 ,  H03K3/00

    CPC分类号： H03K3/037

    摘要： A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal.

    摘要翻译： 电路装置包括用于接收复位控制信号的第一输入和耦合到锁存器的输出的第二输入。 电路装置还包括逻辑电路，其适于响应于接收到复位控制信号而基于输出的状态有条件地重置锁存器。

    Address Multiplexing in Pseudo-Dual Port Memory
    4.
    发明申请
    Address Multiplexing in Pseudo-Dual Port Memory 有权
    伪双端口存储器中的地址复用

    公开(公告)号：US20110051537A1

    公开(公告)日：2011-03-03

    申请号：US12814682

    申请日：2010-06-14

    申请人： ChangHo Jung ,  Cheng Zhong

    发明人： ChangHo Jung ,  Cheng Zhong

    IPC分类号： G11C8/18 ,  G11C7/22

    CPC分类号： G11C7/1072 ,  G11C7/22

    摘要： A pseudo-dual port memory address multiplexing system includes a control circuit operative to identify a read request and a write request to be accomplished during a single clock cycle. A self time tracking circuit monitors a read operation and generates a switching signal when the read operation is determined to be complete. A multiplexer is responsive to the switching signal for selectively providing a read address and a write address to a memory address unit at the proper time.

    摘要翻译： 伪双端口存储器地址复用系统包括控制电路，其操作用于识别在单个时钟周期期间要完成的读请求和写请求。 当读取操作被确定为完成时，自身时间跟踪电路监视读取操作并产生切换信号。 复用器响应于切换信号，用于在适当的时间选择性地向存储器地址单元提供读取地址和写入地址。

    System and Method of Conditional Control of Latch Circuit Devices
    5.
    发明申请
    System and Method of Conditional Control of Latch Circuit Devices 有权
    锁存电路器件的条件控制系统与方法

    公开(公告)号：US20090174453A1

    公开(公告)日：2009-07-09

    申请号：US11971353

    申请日：2008-01-09

    申请人： Hari Rao ,  Cheng Zhong ,  Zhiqin Chen

    发明人： Hari Rao ,  Cheng Zhong ,  Zhiqin Chen

    IPC分类号： H03K3/00

    CPC分类号： H03K3/037

    摘要： A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal.

    摘要翻译： 电路装置包括用于接收复位控制信号的第一输入和耦合到锁存器的输出的第二输入。 电路装置还包括逻辑电路，其适于响应于接收到复位控制信号而基于输出的状态有条件地重置锁存器。

    Memory bit line leakage repair
    6.
    发明授权
    Memory bit line leakage repair 有权
    内存位线泄漏维修

    公开(公告)号：US06950359B2

    公开(公告)日：2005-09-27

    申请号：US10403101

    申请日：2003-03-28

    申请人： Nan Chen ,  Cheng Zhong ,  Mehdi Hamidi Sani

    发明人： Nan Chen ,  Cheng Zhong ,  Mehdi Hamidi Sani

    IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/50

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/83 ,  G11C29/832 ,  G11C2029/5006

    摘要： Techniques for replacing and eliminating paths causing channel leakage current. In one embodiment, one or more precharge enable transistors and a precharge enable signal are added to a circuit configuration. The precharge enable transistors are designed to remain on and simply pass a signal in a properly functioning path. When a leakage path is identified, such as during IDDQ testing, the precharge enable signal is set to turn off the precharge enable transistors. When the precharge enable transistors are off, the leakage path is disrupted, and the leakage current stopped. The path may be replaced with a redundant path.

    摘要翻译： 用于替代和消除引起通道泄漏电流的路径的技术。 在一个实施例中，将一个或多个预充电使能晶体管和预充电使能信号加到电路配置中。 预充电使能晶体管被设计为保持在正常功能的路径上并简单地传递信号。 当识别泄漏路径时，例如在IDDQ测试期间，预充电使能信号被设置为关闭预充电使能晶体管。 当预充电使能晶体管截止时，泄漏路径被破坏，并且泄漏电流停止。 可以用冗余路径替换路径。

    Leakage current reduction for CMOS memory circuits
    8.
    发明授权
    Leakage current reduction for CMOS memory circuits 有权
    CMOS存储器电路的泄漏电流降低

    公开(公告)号：US07092307B2

    公开(公告)日：2006-08-15

    申请号：US10641883

    申请日：2003-08-14

    申请人： Nan Chen ,  Cheng Zhong ,  Mehdi Hamidi Sani

    发明人： Nan Chen ,  Cheng Zhong ,  Mehdi Hamidi Sani

    IPC分类号： G11C5/14

    CPC分类号： G11C11/4074 ,  G11C11/413 ,  G11C2207/2227

    摘要： A CMOS integrated circuit (e.g., an SRAM or a DRAM) is partitioned into a core block, a peripheral block, and a retention block. The core block includes circuits (e.g., memory cells) that are powered on at all times and is coupled directly to power supply and circuit ground. The peripheral block includes circuits that may be powered on or off and are coupled to the power supply via a head switch and/or to circuit ground via a foot switch. The switches and the core block may be implemented with high threshold voltage (high-Vt) FET devices to reduce leakage current. The peripheral block may be implemented with low-Vt FET devices for high-speed operation. The retention block includes circuits (e.g., pull-up devices) that maintain signal lines (e.g., word lines) at a predetermined level so that the internal states of the core block are retained when the peripheral block is powered off.

    摘要翻译： CMOS集成电路（例如，SRAM或DRAM）被划分为核心块，外围块和保留块。 核心块包括始终上电并直接耦合到电源和电路接地的电路（例如，存储器单元）。 外围块包括可以通电或断开并且经由头开关耦合到电源和/或经由脚踏开关电路接地的电路。 开关和核心块可以用高阈值电压（高Vt）FET器件来实现，以减少泄漏电流。 外围块可以用用于高速操作的低Vt FET器件来实现。 保持块包括将信号线（例如，字线）保持在预定水平的电路（例如，上拉装置），使得当外围块被断电时，芯块的内部状态被保持。

    Memory bit line leakage repair
    9.
    发明申请
    Memory bit line leakage repair 有权

    公开(公告)号：US20050073893A1

    公开(公告)日：2005-04-07

    申请号：US10403101

    申请日：2003-03-28

    申请人： Nan Chen ,  Cheng Zhong ,  Mehdi Sani

    发明人： Nan Chen ,  Cheng Zhong ,  Mehdi Sani

    IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/50

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/83 ,  G11C29/832 ,  G11C2029/5006

    摘要： Techniques for replacing and eliminating paths causing channel leakage current. In one embodiment, one or more precharge enable transistors and a precharge enable signal are added to a circuit configuration. The precharge enable transistors are designed to remain on and simply pass a signal in a properly functioning path. When a leakage path is identified, such as during IDDQ testing, the precharge enable signal is set to turn off the precharge enable transistors. When the precharge enable transistors are off, the leakage path is disrupted, and the leakage current stopped. The path may be replaced with a redundant path.

    Memory device for resistance-based memory applications
    10.
    发明授权
    Memory device for resistance-based memory applications 有权
    用于基于电阻的存储器应用的存储器件

    公开(公告)号：US08228714B2

    公开(公告)日：2012-07-24

    申请号：US12206933

    申请日：2008-09-09

    申请人： Anosh B. Davierwalla ,  Cheng Zhong ,  Dongkyu Park ,  Mohamed Hassan Abu-Rahma ,  Mehdi Hamidi Sani ,  Sei Seung Yoon

    发明人： Anosh B. Davierwalla ,  Cheng Zhong ,  Dongkyu Park ,  Mohamed Hassan Abu-Rahma ,  Mehdi Hamidi Sani ,  Sei Seung Yoon

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1673

    摘要： In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

    摘要翻译： 在特定实施例中，公开了一种存储器件，其包括存储单元，该存储单元包括耦合到存取晶体管的基于电阻的存储元件。 存取晶体管具有第一氧化物厚度，以使得能够在工作电压下操作存储单元。 存储器件还包括第一放大器，其被配置为将存储器单元耦合到大于电压限制的电源电压，以基于通过存储器单元的电流来产生数据信号。 第一放大器包括具有大于第一氧化物厚度的第二氧化物厚度的钳位晶体管。 钳位晶体管被配置为防止存储器单元处的工作电压超过电压限制。