公开(公告)号：US07962681B2

公开(公告)日：2011-06-14

申请号：US11971353

申请日：2008-01-09

申请人： Hari Rao ,  Cheng Zhong ,  Zhiqin Chen

发明人： Hari Rao ,  Cheng Zhong ,  Zhiqin Chen

IPC分类号： G06F13/00 ,  H03K3/00

CPC分类号： H03K3/037

摘要： A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal.

摘要翻译： 电路装置包括用于接收复位控制信号的第一输入和耦合到锁存器的输出的第二输入。 电路装置还包括逻辑电路，其适于响应于接收到复位控制信号而基于输出的状态有条件地重置锁存器。

公开(公告)号：US20090174453A1

公开(公告)日：2009-07-09

申请号：US11971353

申请日：2008-01-09

申请人： Hari Rao ,  Cheng Zhong ,  Zhiqin Chen

发明人： Hari Rao ,  Cheng Zhong ,  Zhiqin Chen

IPC分类号： H03K3/00

CPC分类号： H03K3/037

摘要： A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal.

摘要翻译： 电路装置包括用于接收复位控制信号的第一输入和耦合到锁存器的输出的第二输入。 电路装置还包括逻辑电路，其适于响应于接收到复位控制信号而基于输出的状态有条件地重置锁存器。

公开(公告)号：US20100226191A1

公开(公告)日：2010-09-09

申请号：US12397142

申请日：2009-03-03

申请人： Changho Jung ,  Nan Chen ,  Cheng Zhong ,  Zhiqin Chen

发明人： Changho Jung ,  Nan Chen ,  Cheng Zhong ,  Zhiqin Chen

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C7/00 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4094 ,  G11C11/413 ,  G11C2207/2227 ,  H03K19/0016

摘要： A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches are added for pre-charge devices to further reduce leakage current.

摘要翻译： 存储器件包括包括存储器单元的核心阵列。 存储器件还包括耦合到芯阵列的头灯和正电源电压。 磁头开关通过将磁芯阵列与正电源电压断开来减少来自磁芯阵列的漏电流。 另外，增加头开关用于预充电器件，以进一步减少泄漏电流。

公开(公告)号：US08780658B2

公开(公告)日：2014-07-15

申请号：US12397142

申请日：2009-03-03

申请人： Chang Ho Jung ,  Nan Chen ,  Cheng Zhong ,  Zhiqin Chen

发明人： Chang Ho Jung ,  Nan Chen ,  Cheng Zhong ,  Zhiqin Chen

IPC分类号： G11C7/00 ,  G11C5/14 ,  G11C11/4094 ,  G11C7/22 ,  H03K19/00

CPC分类号： G11C7/00 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4094 ,  G11C11/413 ,  G11C2207/2227 ,  H03K19/0016

摘要： A memory device includes a core array that includes memory cells. The memory device also includes a headswitch coupled to the core array and a positive supply voltage. The headswitch reduces leakage current from the core array by disconnecting the core array from the positive supply voltage. Additionally, head switches are added for pre-charge devices to further reduce leakage current.

摘要翻译： 存储器件包括包括存储器单元的核心阵列。 存储器件还包括耦合到芯阵列的头灯和正电源电压。 磁头开关通过将磁芯阵列与正电源电压断开来减少来自磁芯阵列的漏电流。 另外，增加头开关用于预充电器件，以进一步减少泄漏电流。

公开(公告)号：US08270239B2

公开(公告)日：2012-09-18

申请号：US12330747

申请日：2008-12-09

申请人： Nan Chen ,  Changho Jung ,  Zhiqin Chen

发明人： Nan Chen ,  Changho Jung ,  Zhiqin Chen

IPC分类号： G11C29/50 ,  G11C29/06 ,  G11C29/00 ,  G11C11/41 ,  G11C11/413 ,  G11C8/08 ,  G11C7/12

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/24 ,  G11C2029/1204

摘要： A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode.

摘要翻译： 提供一种在半导体存储器件上执行应力测试的半导体存储器件和方法。 在一个示例中，半导体存储器件包括复用器装置，其被配置为在应力模式期间将控制半导体存储器件的内部定时的定时信号从内部信号切换到外部信号，并且还包括一个或多个字线 在应力模式期间接收应力电压的半导体存储器件，基于外部信号的应力模式的持续时间。 在另一示例中，半导体存储器件包括被配置为在应力模式期间接收应力电压的一个或多个字线，以及被配置为在应力模式期间向半导体存储器件的位线提供预充电电压的预充电电路。

公开(公告)号：US08208316B2

公开(公告)日：2012-06-26

申请号：US12194142

申请日：2008-08-19

申请人： Nan Chen ,  Chang Jung ,  Zhiqin Chen

发明人： Nan Chen ,  Chang Jung ,  Zhiqin Chen

IPC分类号： G11C7/06

CPC分类号： G11C7/12 ,  G11C11/409 ,  G11C2207/005

摘要： A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line.

摘要翻译： 针对存储器阵列中的读取路径改进了检测边缘。 实施例通过在读列多路复用器中使用具有较低阈值电压的门来提高感测余量。 交叉耦合保持器可以通过增加存储高值的位线上的电压电平来进一步提高感测容限，从而抵消“高”位线上的泄漏。

公开(公告)号：US20090231934A1

公开(公告)日：2009-09-17

申请号：US12048676

申请日：2008-03-14

申请人： Chang Ho Jung ,  Nan Chen ,  Zhiqin Chen

发明人： Chang Ho Jung ,  Nan Chen ,  Zhiqin Chen

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/14 ,  G11C7/08 ,  G11C7/22

摘要： A method accurately tracks a bit line maturing time for compiler memory. The method includes enabling a dummy word line in response to an internal clock signal. The dummy word line is enabled prior to enabling a real word line. A dummy bit line is matured in response to enabling of the dummy word line. The dummy bit line matures at a same rate that a real bit line matures. The method also includes disabling the dummy word line in response to determining a threshold voltage differential based on monitoring maturation of the dummy bit line. The real word line is enabled a predefined delay after enabling of the dummy word line. Similarly, the word line is disabled the predefined delay after disabling of the dummy word line. In response to disabling the dummy word line, a sense enable signal is generated.

摘要翻译： 一种方法准确地跟踪编译器存储器的位线成熟时间。 该方法包括响应于内部时钟信号启用伪字线。 虚拟字线在启用实际字线之前被使能。 虚拟位线响应于虚拟字线的使能而成熟。 虚拟位线以与实际位线成熟的相同速率成熟。 该方法还包括响应于基于虚拟位线的监视成熟确定阈值电压差来禁用该虚拟字线。 在使能虚拟字线之后，实际字线被启用预定义的延迟。 类似地，在禁用虚拟字线之后，字线被禁用预定义的延迟。 响应于禁用虚拟字线，产生感测使能信号。

公开(公告)号：US20080037338A1

公开(公告)日：2008-02-14

申请号：US11614828

申请日：2006-12-21

申请人： Zhiqin Chen ,  Chang Ho Jung

发明人： Zhiqin Chen ,  Chang Ho Jung

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/14 ,  G11C7/222 ,  G11C11/41 ,  G11C11/417 ,  G11C29/02 ,  G11C29/023

摘要： A memory has a novel self-timing circuit that generates internal memory control signals. Control signals may include an address latch enable signal, a decoder enable signal, and a sense amplifier enable signal. The circuit has a timing loop whose timing mimics the timing of an access of the real memory. The timing loop includes dummy bit cells of identical construction to bit cells in the real array being accessed, a programmable delay circuit, and a programmable accelerator circuit. The dummy bit cells cause the timing of the control signals to track speed changes in the memory array being accessed. The programmable delay and accelerator circuits are usable to slow or speed the timing loop. The programmable delay and accelerator circuits are usable to achieve a desired yield to memory access speed tradeoff. Flexibility of the timing loop allows a memory to be designed before memory access timing characteristics are fixed.

摘要翻译： 存储器具有产生内部存储器控制信号的新型自定时电路。 控制信号可以包括地址锁存使能信号，解码器使能信号和读出放大器使能信号。 该电路具有定时循环，其定时模拟实际存储器的访问定时。 定时回路包括与要访问的实数阵列中的位单元相同结构的虚拟位单元，可编程延迟电路和可编程加速器电路。 虚拟位单元使得控制信号的定时跟踪所访问的存储器阵列中的速度变化。 可编程延迟和加速器电路可用于减慢或加速定时回路。 可编程延迟和加速器电路可用于实现对存储器访问速度权衡的期望收益。 定时循环的灵活性允许在存储器访问定时特性固定之前设计存储器。

公开(公告)号：US08564365B2

公开(公告)日：2013-10-22

申请号：US13469261

申请日：2012-05-11

申请人： Nam V. Dang ,  Terrence B. Remple ,  Zhiqin Chen

发明人： Nam V. Dang ,  Terrence B. Remple ,  Zhiqin Chen

IPC分类号： H03K9/08

CPC分类号： H03K9/08 ,  H04L25/4902

摘要： A pulse width modulated (PWM) signal is received and, over a time interval of the PWM signal, a first count is incremented when the PWM signal is at a first level, and a second count is incremented when the PWM signal is at a second level. At the end of time interval the first count is compared to the second count and, based on the comparison, a decoded bit is generated. Optionally, incrementing the first count is by enabling a first oscillator that increments a first counter, and incrementing the second count is by enabling a second oscillator that increments a second counter.

摘要翻译： 接收脉宽调制（PWM）信号，并且在PWM信号的时间间隔中，当PWM信号处于第一电平时，第一计数增加，并且当PWM信号为第二时，第二计数增加 水平。 在时间间隔结束时，将第一计数与第二计数进行比较，并且基于比较，生成解码位。 可选地，增加第一计数是通过启用增加第一计数器的第一振荡器，并且通过启用增加第二计数器的第二振荡器来递增第二计数。

公开(公告)号：US20100146320A1

公开(公告)日：2010-06-10

申请号：US12328283

申请日：2008-12-04

申请人： Nan Chen ,  Zhiqin Chen ,  Varun Verma

发明人： Nan Chen ,  Zhiqin Chen ,  Varun Verma

IPC分类号： G06F1/12 ,  G06F1/14

CPC分类号： G11C29/50 ,  G01R31/31725 ,  G11C7/22 ,  G11C29/50012 ,  G11C29/56 ,  G11C29/56012

摘要： Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews.

摘要翻译： 提供了用于确定存储器访问时间的方法和系统。 在存储器使用的第一时钟信号和用作参考时钟信号的第二时钟信号之间测量第一相位偏移。 然后，当存储器完成给定读取操作和第二时钟信号时，在由存储器输出的第一时钟信号的延迟版本之间测量第二相位偏移。 存储器访问时间基于第一和第二相位偏移来确定。