公开(公告)号：US08946071B2

公开(公告)日：2015-02-03

申请号：US14364950

申请日：2012-03-23

申请人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

发明人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L21/823814 ,  H01L21/2255 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a substrate; forming a source/drain region and a gate sidewall spacer at both sides of the gate stacked structure; depositing a Nickel-based metal layer at least in the source/drain region; performing a first annealing so that the silicon in the source/drain region reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase metal silicide is transformed into a Nickel-based metal silicide, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide and the source/drain region. The method according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH of the metal-semiconductor contact between the Nickel-based metal silica and the source/drain region is effectively reduced, the contact resistance is decreased, and the driving capability of the device is improved.

摘要翻译： 本发明公开了一种半导体器件的制造方法，包括：在基板上形成栅叠层结构; 在栅极层叠结构的两侧形成源极/漏极区域和栅极侧壁间隔物; 至少在源/漏区中沉积镍基金属层; 进行第一退火，使得源极/漏极区中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使富Ni相的金属硅化物转变为镍系金属硅化物，同时在镍基金属硅化物与源极/漏极区之间的界面处形成掺杂离子的偏析区域 。 根据本发明的方法在将掺杂离子注入到金属硅化物的富Ni相中之后执行退火，从而提高掺杂离子的固溶度并形成高度浓缩的掺杂离子的偏析区，因此SBH 镍基金属二氧化硅和源极/漏极区域之间的金属 - 半导体接触被有效地降低，接触电阻降低，并且器件的驱动能力得到改善。

公开(公告)号：US08642433B2

公开(公告)日：2014-02-04

申请号：US13509551

申请日：2011-12-05

申请人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L21/336 ,  H01L21/477

CPC分类号： H01L29/6653 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.

摘要翻译： 公开了一种制造半导体器件的方法，包括：提供衬底，衬底上的栅极区域和栅极区两侧的半导体区域; 在所述栅极区域的侧壁上形成覆盖所述半导体区域的一部分的牺牲间隔物; 在牺牲间隔物外部和栅极区域上的半导体区域的一部分上形成金属层; 去除牺牲隔离物; 进行退火，使得金属层与半导体区域反应，以在半导体区域上形成金属 - 半导体化合物层; 并除去未反应的金属层。 通过将金属层与器件的栅极区域与牺牲间隔物的厚度分开，金属层扩散对沟道和栅极区域的影响降低，并且器件的性能得到改善。

公开(公告)号：US20130045588A1

公开(公告)日：2013-02-21

申请号：US13509551

申请日：2011-12-05

申请人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

发明人： Huicai Zhong ,  Jun Luo ,  Chao Zhao ,  Qingqing Liang

IPC分类号： H01L21/20

CPC分类号： H01L29/6653 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device is disclosed, comprising: providing a substrate, a gate region on the substrate and a semiconductor region at both sides of the gate region; forming sacrificial spacers, which cover a portion of the semiconductor region, on sidewalls of the gate region; forming a metal layer on a portion of the semiconductor region outside the sacrificial spacers and on the gate region; removing the sacrificial spacers; performing annealing so that the metal layer reacts with the semiconductor region to form a metal-semiconductor compound layer on the semiconductor region; and removing unreacted metal layer. By separating the metal layer from the channel and the gate region of the device with the thickness of the sacrificial spacers, the effect of metal layer diffusion on the channel and the gate region is reduced and performance of the device is improved.

摘要翻译： 公开了一种制造半导体器件的方法，包括：提供衬底，衬底上的栅极区域和栅极区两侧的半导体区域; 在所述栅极区域的侧壁上形成覆盖所述半导体区域的一部分的牺牲间隔物; 在牺牲间隔物外部和栅极区域上的半导体区域的一部分上形成金属层; 去除牺牲隔离物; 进行退火，使得金属层与半导体区域反应，以在半导体区域上形成金属 - 半导体化合物层; 并除去未反应的金属层。 通过将金属层与器件的栅极区域与牺牲间隔物的厚度分开，金属层扩散对沟道和栅极区域的影响降低，并且器件的性能得到改善。

公开(公告)号：US09070719B2

公开(公告)日：2015-06-30

申请号：US13577942

申请日：2011-11-18

申请人： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/84

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

摘要翻译： 公开了一种半导体器件结构，其制造方法和半导体鳍片的制造方法。 在一个实施例中，制造半导体器件结构的方法包括：在半导体衬底上沿第一方向形成翅片; 在第二方向上形成栅极线，在半导体衬底上与第一方向交叉的第二方向和与鳍状物交叉的栅极线与夹在栅极线和鳍之间的栅极电介质层形成栅极线; 形成围绕所述栅极线的介电隔离层; 以及在预定位置执行器件间电隔离，其中所述栅极线的隔离部分形成各个器件的独立栅电极。

公开(公告)号：US08987127B2

公开(公告)日：2015-03-24

申请号：US14361944

申请日：2012-03-23

申请人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

发明人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L21/283

CPC分类号： H01L21/28097 ,  H01L21/283 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。 根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域， 因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。

公开(公告)号：US20120156873A1

公开(公告)日：2012-06-21

申请号：US13063922

申请日：2011-01-27

申请人： Jun Luo ,  Chao Zhao ,  Huicai Zhong

发明人： Jun Luo ,  Chao Zhao ,  Huicai Zhong

IPC分类号： H01L21/28

CPC分类号： H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

摘要： A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer.

摘要翻译： 一种用于限制金属硅化物向通道区域的横向侵入的方法，包括：提供半导体衬底，形成在半导体衬底上的栅堆叠，形成在栅叠层一侧的半导体中的源区， 漏极区域形成在栅极堆叠的另一侧上的半导体衬底中; 在所述栅极堆叠和所述半导体衬底上形成牺牲隔离物; 沉积用于覆盖半导体衬底，栅极堆叠和牺牲隔离物的金属层; 对所述半导体基板进行热处理，由此使所述金属层与所述源极区域和所述漏极区域中的所述牺牲隔离物和所述半导体基板反应; 去除牺牲间隔物，牺牲间隔物和金属层的反应产物，以及不与牺牲间隔物反应的金属层的一部分。

公开(公告)号：US20140302644A1

公开(公告)日：2014-10-09

申请号：US14361944

申请日：2012-03-23

申请人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

发明人： Jun Luo ,  Chao Zhao ,  Huicai Zhong ,  Junfeng Li ,  Dapeng Chen

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L29/66

CPC分类号： H01L21/28097 ,  H01L21/283 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate. The method for manufacturing the semiconductor device according to the present invention performs the annealing after implanting the doping ions into the Ni-rich phase of metal silicide, thereby improving the solid solubility of the doping ions and forming a segregation region of highly concentrated doping ions, thus the SBH between the Nickel-based metal silicide and the silicon channel is effectively reduced, and the driving capability of the device is improved.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括：在硅衬底上形成栅层叠结构; 在基板上沉积镍基金属层和栅极堆叠结构; 进行第一退火，使得衬底中的硅与镍基金属层反应形成金属硅化物的富Ni相; 通过将掺杂离子注入到金属硅化物的富Ni相中来进行离子注入; 进行第二退火，使得金属与硅化物的富Ni相转变为镍基金属硅化物源极/漏极，同时在镍基金属硅化物源之间的界面处形成掺杂离子的偏析区域 /漏极和衬底。 根据本发明的制造半导体器件的方法在将掺杂离子注入到金属硅化物的富Ni相中之后进行退火，从而提高掺杂离子的固溶度并形成高浓度掺杂离子的偏析区域， 因此有效地降低了镍基金属硅化物与硅通道之间的SBH，提高了器件的驱动能力。

公开(公告)号：US08536053B2

公开(公告)日：2013-09-17

申请号：US13063922

申请日：2011-01-27

申请人： Jun Luo ,  Chao Zhao ,  Huicai Zhong

发明人： Jun Luo ,  Chao Zhao ,  Huicai Zhong

IPC分类号： H01L21/28

CPC分类号： H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545

摘要： A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer.

摘要翻译： 一种用于限制金属硅化物向通道区域的横向侵入的方法，包括：提供半导体衬底，形成在半导体衬底上的栅堆叠，形成在栅叠层一侧的半导体中的源区， 漏极区域形成在栅极堆叠的另一侧上的半导体衬底中; 在所述栅极堆叠和所述半导体衬底上形成牺牲隔离物; 沉积用于覆盖半导体衬底，栅极堆叠和牺牲间隔物的金属层; 对所述半导体基板进行热处理，由此使所述金属层与所述源极区域和所述漏极区域中的所述牺牲隔离物和所述半导体基板反应; 去除牺牲间隔物，牺牲间隔物和金属层的反应产物，以及不与牺牲间隔物反应的金属层的一部分。

公开(公告)号：US20130221414A1

公开(公告)日：2013-08-29

申请号：US13697319

申请日：2012-03-26

申请人： Chao Zhao ,  Jun Luo ,  Huicai Zhong

发明人： Chao Zhao ,  Jun Luo ,  Huicai Zhong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： The present invention provides a semiconductor FET and a method for manufacturing the same. The semiconductor FET may comprise: a gate wall; a fin outside the gate wall, both ends of the fin being connected with the source/drain regions on both ends of the fin; and a contact wall on both sides of the gate wall, the contact wall being connected with the source/drain regions via the underlying silicide layer, wherein an airgap is provided around the gate wall. Since an airgap is formed around the gate wall, and particularly the airgap is formed between the gate wall and the contact wall, it is possible to decrease the parasitic capacitance between the gate wall and the contact wall. As a result, the problem of excessive parasitic capacitance resulting from use of the contact wall can be effectively alleviated.

摘要翻译： 本发明提供一种半导体FET及其制造方法。 半导体FET可以包括：栅极壁; 在门壁外的翅片，翅片的两端与翅片两端的源极/漏极区域连接; 以及在栅极壁的两侧上的接触壁，所述接触壁经由下面的硅化物层与源极/漏极区域连接，其中在栅极壁周围设置气隙。 由于在栅极壁周围形成气隙，特别是在栅极壁和接触壁之间形成气隙，因此能够降低栅极壁与接触壁之间的寄生电容。 结果，可以有效地缓解由使用接触壁引起的过大的寄生电容的问题。

公开(公告)号：US20130062708A1

公开(公告)日：2013-03-14

申请号：US13577942

申请日：2011-11-18

申请人： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

发明人： Huicai Zhong ,  Qingqing Liang ,  Jun Luo ,  Chao Zhao

IPC分类号： H01L21/762 ,  H01L27/088

CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785

摘要： A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.

摘要翻译： 公开了一种半导体器件结构，其制造方法和半导体鳍片的制造方法。 在一个实施例中，制造半导体器件结构的方法包括：在半导体衬底上沿第一方向形成翅片; 在第二方向上形成栅极线，在半导体衬底上与第一方向交叉的第二方向和与鳍状物交叉的栅极线与夹在栅极线和鳍之间的栅极电介质层形成栅极线; 形成围绕所述栅极线的介电隔离层; 以及在预定位置执行器件间电隔离，其中所述栅极线的隔离部分形成各个器件的独立栅电极。