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84 条记录 (耗时 0.024 秒)

    Network packet buffer allocation optimization in memory bank systems
    1.
    发明授权
    Network packet buffer allocation optimization in memory bank systems 失效
    存储器系统中的网络数据包缓冲区分配优化

    公开(公告)号：US07158438B2

    公开(公告)日：2007-01-02

    申请号：US11092010

    申请日：2005-03-29

    申请人： Chen-Chi Kuo ,  Senthil Nathan Arunachalam ,  Sridhar Lakshmanamurthy ,  Uday Naik

    发明人： Chen-Chi Kuo ,  Senthil Nathan Arunachalam ,  Sridhar Lakshmanamurthy ,  Uday Naik

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1042

    摘要： An arrangement of buffer in a memory unit including a plurality of memory banks may store information in rows that span the memory banks. Moreover, a processor may be adapted to (i) establish a plurality of buffers to be associated with the memory unit, wherein the size of each buffer is less than the width of a memory bank, and (ii) arrange for a selected buffer to begin in a memory bank other than a memory bank in which a previously selected buffer begins.

    摘要翻译： 包括多个存储体的存储器单元中的缓冲器的布置可以以跨越存储体的行存储信息。 此外，处理器可以适于（i）建立与存储器单元相关联的多个缓冲器，其中每个缓冲器的大小小于存储体的宽度，并且（ii）将所选择的缓冲器设置为 开始于存储库，而不是先前选择的缓冲区开始的存储体。

    APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMORY CONTROLLERS
    6.
    发明申请
    APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMORY CONTROLLERS 有权
    从分布式存储器控制器中合并和对齐数据的装置和方法

    公开(公告)号：US20090132773A1

    公开(公告)日：2009-05-21

    申请号：US12356284

    申请日：2009-01-20

    申请人： Rohit Natarajan ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo

    发明人： Rohit Natarajan ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo

    IPC分类号： G06F12/06

    CPC分类号： G06F13/1684

    摘要： We describe a system and method to merge and align data from distributed memory controllers. A memory system includes a command bus to transmit a predetermined memory access command, and a memory interface to manipulate data from at least two memory channels, each memory channel corresponding to a portion of a distributed memory, responsive to the predetermined memory access command. The memory interface includes a plurality of memory controllers coupled to the command bus, each memory controller being operable to control a corresponding memory channel responsive to the predetermined memory access command, and a push arbiter coupled to each memory controller. The push arbiter being is operable to merge and align data retrieved responsive to each split read align command.

    摘要翻译： 我们描述一种从分布式存储器控制器合并和对齐数据的系统和方法。 存储器系统包括用于发送预定存储器访问命令的命令总线，以及存储器接口，用于响应于预定的存储器访问命令，操作来自至少两个存储器通道的数据，每个存储器通道对应于分布式存储器的一部分。 存储器接口包括耦合到命令总线的多个存储器控制器，每个存储器控制器可操作以响应于预定存储器访问命令来控制相应的存储器通道，以及耦合到每个存储器控制器的推送仲裁器。 推送仲裁器可操作以合并和对准根据每个拆分读取对准命令检索的数据。

    Packet assembly
    8.
    发明申请
    Packet assembly 失效
    数据包组装

    公开(公告)号：US20050135353A1

    公开(公告)日：2005-06-23

    申请号：US10742189

    申请日：2003-12-18

    申请人： Prashant Chandra ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo ,  Rohit Natarajan ,  Mark Rosenbluth

    发明人： Prashant Chandra ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo ,  Rohit Natarajan ,  Mark Rosenbluth

    IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08

    CPC分类号： H04L69/166 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9042 ,  H04L49/9052 ,  H04L67/02 ,  H04L69/16 ,  H04L69/329 ,  H04L2012/5652

    摘要： In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.

    摘要翻译： 通常，在一个方面，本公开描述了一种在存储器中组装分组的方法。 该方法包括读取分组到多个分组的分组的第一分段中的数据，并向存储器控制器发出命令，该命令使得存储器控制器将读取的数据的子集移位并写入耦合到存储器控制器的存储器。 该方法还包括将剩余的读取数据保存为第一残余，检索包含在分组的第二段中的数据，以及将所检索的数据和第一残差的至少一部分写入存储器。

    Engine for comparing a key with rules having high and low values defining a range
    10.
    发明授权
    Engine for comparing a key with rules having high and low values defining a range 失效
    用于将密钥与定义范围的高和低值的规则进行比较的引擎

    公开(公告)号：US07340570B2

    公开(公告)日：2008-03-04

    申请号：US10921547

    申请日：2004-08-18

    申请人： Sridhar Lakshmanamurthy ,  Chang-Ming P. Lin ,  Subramanian Anand ,  Chen-Chi Kuo ,  Alok Kumar

    发明人： Sridhar Lakshmanamurthy ,  Chang-Ming P. Lin ,  Subramanian Anand ,  Chen-Chi Kuo ,  Alok Kumar

    IPC分类号： G06F12/00 ,  H04L12/28

    CPC分类号： H04L47/10 ,  H04L45/742 ,  H04L47/2441

    摘要： Provided is an engine for comparing a key with rules having defined ranges. A key is received and a rule is accessed including a high and low values defining a range. The key is concurrently compared with the high and low values to determine whether the key falls within a range defined by the high and low values an indication is made in status information the rule in response to the key falling within the defined range of the rule. An additional iteration of accessing a next rule is performed to concurrently compare the key with the high and low values of the next rule, and indication is made in the status information of the next rule in response to the key falling within a range defined by the next rule.

    摘要翻译： 提供了一种用于将密钥与具有限定范围的规则进行比较的引擎。 接收到密钥并访问规则，包括定义范围的高和低值。 密钥同时与高和低值进行比较，以确定密钥是否落在由高和低值定义的范围内，在状态信息中指示响应于规则中规定的密钥的规则。 执行访问下一个规则的附加迭代以将密钥与下一个规则的高和低值并行地进行比较，并且响应于键落在由下一个规则定义的范围内的下一个规则的状态信息中进行指示 下一条规则。