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    Fabrication of FinFETs with multiple fin heights
    3.
    发明授权
    Fabrication of FinFETs with multiple fin heights 有权
    具有多个翅片高度的FinFET的制造

    公开(公告)号：US07612405B2

    公开(公告)日：2009-11-03

    申请号：US11714644

    申请日：2007-03-06

    申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu

    发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chu-Yun Fu ,  Yu-Rung Hsu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

    摘要： A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.

    摘要翻译： 半导体结构包括从半导体衬底的顶表面延伸到半导体衬底中的第一半导体条，其中第一半导体条具有第一高度。 第一绝缘区域形成在半导体衬底中并围绕第一半导体条的底部，其中第一绝缘区具有比第一半导体条的顶表面低的第一顶表面。 第二半导体条从半导体衬底的顶表面延伸到半导体衬底中，其中第二半导体条的第二高度大于第一高度。 第二绝缘区域形成在半导体衬底中并围绕第二半导体条的底部，其中第二绝缘区域具有比第一顶表面低的第二顶表面，并且其中第一绝缘区域和第二绝缘区域基本相同 厚度

    Germanium FinFETs Having Dielectric Punch-Through Stoppers
    5.
    发明申请
    Germanium FinFETs Having Dielectric Punch-Through Stoppers 有权
    具有介质穿孔塞的锗FinFET

    公开(公告)号：US20120025313A1

    公开(公告)日：2012-02-02

    申请号：US13272994

    申请日：2011-10-13

    申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

    发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

    IPC分类号： H01L27/12 ,  H01L29/02

    CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

    摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

    摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

    Germanium FinFETs having dielectric punch-through stoppers
    6.
    发明授权
    Germanium FinFETs having dielectric punch-through stoppers 有权
    锗FinFET具有绝缘穿孔塞

    公开(公告)号：US08048723B2

    公开(公告)日：2011-11-01

    申请号：US12329279

    申请日：2008-12-05

    申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

    发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

    IPC分类号： H01L21/332

    CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

    摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

    摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以形成包括硅片和在硅微细上的冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

    Reducing Resistance in Source and Drain Regions of FinFETs
    7.
    发明申请
    Reducing Resistance in Source and Drain Regions of FinFETs 有权
    降低FinFET源极和漏极区域的电阻

    公开(公告)号：US20090095980A1

    公开(公告)日：2009-04-16

    申请号：US11873156

    申请日：2007-10-16

    申请人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

    发明人： Chen-Hua Yu ,  Yu-Rung Hsu ,  Chen-Nan Yeh ,  Cheng-Hung Chang

    IPC分类号： H01L29/778 ,  H01L29/786

    CPC分类号： H01L29/1033 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

    摘要： A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer.

    摘要翻译： 半导体结构包括在基板的顶面上的半导体翅片，其中半导体鳍片包括具有第一宽度的中间部分; 以及连接到中间部分的相对端部的第一和第二端部分，其中第一和第二端部部分至少包括具有大于第一宽度的第二宽度的顶部部分。 半导体结构还包括在半导体鳍片的顶表面和中间部分的侧壁上的栅介质层; 以及栅极电介质层上的栅电极。

    Germanium FinFETs having dielectric punch-through stoppers
    8.
    发明授权
    Germanium FinFETs having dielectric punch-through stoppers 有权
    锗FinFET具有绝缘穿孔塞

    公开(公告)号：US08957477B2

    公开(公告)日：2015-02-17

    申请号：US13272994

    申请日：2011-10-13

    申请人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

    发明人： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

    IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/02

    CPC分类号： H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

    摘要： A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

    摘要翻译： 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

    System and Method for Source/Drain Contact Processing
    9.
    发明申请
    System and Method for Source/Drain Contact Processing 有权
    源/排水接触处理系统和方法

    公开(公告)号：US20110171805A1

    公开(公告)日：2011-07-14

    申请号：US13027436

    申请日：2011-02-15

    申请人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

    发明人： Chen-Hua Yu ,  Cheng-Hung Chang ,  Chen-Nan Yeh ,  Yu-Rung Hsu

    IPC分类号： H01L21/336 ,  H01L21/28

    CPC分类号： H01L29/785 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7843 ,  H01L2029/7858

    摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

    摘要翻译： 公开了用于降低接触电阻并防止由于接触不对准引起的变化的系统和方法。 优选实施例包括具有位于鳍内的源/漏区的非平面晶体管。 层间电介质覆盖非平面晶体管，并且通过层间电介质将触点形成到源/漏区。 接触件优选地与翅片的多个表面接触，以增加接触件和翅片之间的接触面积。