公开(公告)号：US06833323B2

公开(公告)日：2004-12-21

申请号：US10354710

申请日：2003-01-29

申请人： Chen-Hua Yui ,  Tsu Shih

发明人： Chen-Hua Yui ,  Tsu Shih

IPC分类号： H01L21302

CPC分类号： H01L21/3212 ,  H01L21/7684

摘要： A method for preventing peeling of a metal layer formed over a semiconductor wafer process surface during a chemical mechanical polishing (CMP) process including providing a semiconductor wafer having a process surface comprising a periphery portion and a central portion said central portion including active areas having semiconductor devices features formed therein the process surface including a dielectric insulating layer; forming a plurality of openings in the periphery portion to form closed communication with the dielectric insulating layer the plurality of openings having an aspect ratio of at least 2; blanket depositing a metal layer to cover the process surface including the periphery portion to include filling the plurality of openings to anchor the metal layer; and, performing a CMP process to remove at least a portion of the metal layer from the process surface.

摘要翻译： 一种用于在化学机械抛光（CMP）工艺过程中防止在半导体晶片工艺表面上形成的金属层的剥离的方法，包括提供具有包括周边部分和中心部分的工艺表面的半导体晶片，所述中间部分包括具有半导体的有源区域 在其中形成的处理表面的器件特征包括介电绝缘层; 在所述周边部分中形成多个开口以与所述电介质绝缘层形成与所述多个开口具有至少2的纵横比的闭合连通; 毯子沉积金属层以覆盖包括周边部分的处理表面，以包括填充多个开口以锚定金属层; 以及执行CMP处理以从处理表面去除金属层的至少一部分。

公开(公告)号：US06686284B2

公开(公告)日：2004-02-03

申请号：US10072244

申请日：2002-02-06

申请人： Chi-Wei Chung ,  Tung-Ching Tseng ,  Tsu Shih ,  Syun-Ming Jang

发明人： Chi-Wei Chung ,  Tung-Ching Tseng ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： H01L2100

CPC分类号： H01L21/3212 ,  B24B37/32 ,  B24B55/02 ,  H01L21/31053

摘要： A chemical mechanical polishing apparatus that is equipped with a chilled retaining ring and a method for using the apparatus are described. The retaining ring is mounted therein a heat transfer means such as a metal tube and flowing therethrough a heat exchanging fluid for carrying away heat from the wafer mounted in the retaining ring, resulting in a temperature reduction in the slurry solution that contacts the wafer. The present invention apparatus and method therefore reduces the delamination problem for low k dielectric materials during polishing and the wafer scratching problem.

摘要翻译： 描述了配备有冷冻保持环的化学机械抛光装置和使用该装置的方法。 保持环安装有诸如金属管的传热装置，并在其中流过用​​于从安装在保持环中的晶片携带热量的热交换流体，导致与晶片接触的浆液中的温度降低。 因此，本发明的装置和方法减少了抛光期间低k电介质材料和晶片划伤问题的分层问题。

公开(公告)号：US06638868B1

公开(公告)日：2003-10-28

申请号：US10141221

申请日：2002-05-07

申请人： Tsu Shih ,  Kun Ku Hung ,  Wen-Hun Tung ,  Wen-Chin Chiou

发明人： Tsu Shih ,  Kun Ku Hung ,  Wen-Hun Tung ,  Wen-Chin Chiou

IPC分类号： H01L21302

CPC分类号： B24B37/046 ,  B24B37/042 ,  H01L21/02071 ,  H01L21/3212 ,  H01L21/7684

摘要： A method and apparatus for implementing the method for preventing or reducing corrosion of copper containing features included in a semiconductor wafer in a chemical mechanical polishing (CMP) process the method providing at least one semiconductor wafer polishing surface including copper filled anisotropically etched features; polishing the at least one semiconductor wafer polishing surface according to a CMP process having a polishing pad surface contacting the at least one it semiconductor wafer polishing surface at least a portion of the polishing pad in electrically conductive communication with a conductive polishing platen; and, providing at least one electrically conductive pathway from the conductive polishing platen.

摘要翻译： 一种用于在化学机械抛光（CMP）工艺中实现用于防止或减少包含在半导体晶片中的含铜特征的腐蚀的方法和装置，该方法提供至少一个包括铜填充的各向异性蚀刻特征的半导体晶片抛光表面的方法; 根据CMP工艺抛光所述至少一个半导体晶片抛光表面，所述CMP工艺具有抛光垫表面，所述抛光垫表面与所述至少一个半导体晶片抛光表面接触，所述至少一部分所述抛光垫与导电抛光平台导电连通; 以及从所述导电抛光平台提供至少一个导电通路。

公开(公告)号：US06620034B2

公开(公告)日：2003-09-16

申请号：US10043780

申请日：2002-01-14

申请人： Tsu Shih ,  Jih-Churng Jwu ,  Ying-Ho Chen ,  Syun-Ming Jang

发明人： Tsu Shih ,  Jih-Churng Jwu ,  Ying-Ho Chen ,  Syun-Ming Jang

IPC分类号： B24B100

CPC分类号： B24B37/12 ,  B24B37/015 ,  B24B55/02

摘要： The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.

摘要翻译： 本发明提供了一种方法和装置，其通过在低温下进行CMP工艺，并且通过添加用作腐蚀抑制剂的浆料在CMP工艺期间保持该低温来防止铜线的CMP中的铜离子的累积。

公开(公告)号：US06602780B2

公开(公告)日：2003-08-05

申请号：US09947788

申请日：2001-09-06

申请人： Tsu Shih ,  Yung-Cheng Lu ,  Lih Ping Li ,  Tien-I Bao ,  Chung Chi Ko

发明人： Tsu Shih ,  Yung-Cheng Lu ,  Lih Ping Li ,  Tien-I Bao ,  Chung Chi Ko

IPC分类号： H01L214763

CPC分类号： H01L21/76807 ,  H01L21/76831 ,  H01L2221/1057

摘要： A method for forming a protective oxide liner to reduce a surface reflectance including providing a hydrophilic insulating layer over a conductive layer; providing an anti-reflectance coating (ARC) layer over the hydrophilic insulating layer; providing an etching stop layer over the anti-reflectance coating (ARC) layer; photolithographically defining a pattern on a surface of the etching stop layer for etching; anisotropically etching at least one etch opening extending at least partially through a thickness of the hydrophilic insulating layer; depositing an oxide liner such that the sidewalls and bottom portion of the at least one etch opening and said surface are covered by the oxide liner; and, removing the oxide liner from aid surface according to a chemical mechanical (CMP) process to a surface reflectance.

摘要翻译： 一种用于形成保护性氧化物衬垫以减少表面反射率的方法，包括在导电层上提供亲水性绝缘层; 在所述亲水绝缘层上提供抗反射涂层（ARC）层; 在抗反射涂层（ARC）层上提供蚀刻停止层; 在蚀刻停止层的表面上光刻地限定图案用于蚀刻; 各向异性蚀刻至少一个至少部分延伸穿过亲水性绝缘层的厚度的蚀刻开口; 沉积氧化物衬里，使得所述至少一个蚀刻开口和所述表面的侧壁和底部被所述氧化物衬垫覆盖; 并且根据化学机械（CMP）工艺将氧化物衬垫从辅助表面去除到表面反射率。

公开(公告)号：US06372632B1

公开(公告)日：2002-04-16

申请号：US09490138

申请日：2000-01-24

申请人： Chen-Hua Yu ,  Weng Chang ,  Jih-Chung Twu ,  Tsu Shih

发明人： Chen-Hua Yu ,  Weng Chang ,  Jih-Chung Twu ,  Tsu Shih

IPC分类号： H01L214763

CPC分类号： H01L21/7688 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/7684

摘要： A method of forming a planarized metal interconnect comprising the following steps. A semiconductor structure is provided. A low K dielectric layer is formed over the semiconductor structure. A sacrificial layer over is formed over the low K dielectric layer. The sacrificial layer and low K dielectric layer are patterned to form a trench within the sacrificial layer and low K dielectric layer. A barrier layer is formed over the sacrificial layer, lining the trench side walls and bottom. Metal is deposited on the barrier layer to form a metal layer filling the lined trench and blanket filling the sacrificial layer covered low K dielectric layer. The metal layer and the barrier layer are planarized, exposing the upper surface of the sacrificial layer. The sacrificial layer is removed to form a planarized metal interconnect.

摘要翻译： 一种形成平面化金属互连的方法，包括以下步骤。 提供半导体结构。 在半导体结构上形成低K电介质层。 在低K电介质层上形成牺牲层。 将牺牲层和低K电介质层图案化以在牺牲层和低K电介质层内形成沟槽。 在牺牲层上形成阻挡层，衬在沟槽侧壁和底部。 金属沉积在阻挡层上以形成填充衬里沟槽的金属层，并覆盖填充覆盖低K电介质层的牺牲层。 金属层和阻挡层被平坦化，暴露牺牲层的上表面。 去除牺牲层以形成平坦化的金属互连。

公开(公告)号：US5919714A

公开(公告)日：1999-07-06

申请号：US72990

申请日：1998-05-06

申请人： Jeng-Horng Chen ,  Tsu Shih

发明人： Jeng-Horng Chen ,  Tsu Shih

IPC分类号： G03F7/20 ,  H01L21/00

CPC分类号： G03F7/70633 ,  Y10S438/975

摘要： An improvement in the box-in-box overlay measurement method has been achieved by forming the outer box from a segmented trench comprised of a number of concentric ridges that project upwards from the floor of the trench. When the segmented trench has been overfilled with tungsten (or similar metal) the excess metal is removed using either etch-back or chem. mech. polishing as the planarizing technique. Because of the presence of the ridges, the trench (i.e. the outer box) becomes reproducibly easy to see when the inner box (which will be etched from a second layer deposited on the first one) is being positioned inside it. Furthermore, the tendency for the outer box to be broken in critical places (often seen in the prior art) is now largely eliminated.

公开(公告)号：US5858854A

公开(公告)日：1999-01-12

申请号：US730382

申请日：1996-10-16

申请人： Chao-Chieh Tsai ,  Shun-Liang Hsu ,  Tsu Shih

发明人： Chao-Chieh Tsai ,  Shun-Liang Hsu ,  Tsu Shih

IPC分类号： H01L23/544 ,  H01L21/76

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002

摘要： A method of forming high contrast alignment marks on an integrated circuit wafer for patterning a layer of highly reflective electrode metal is described. A method of patterning a layer of highly reflective metal on an integrated circuit wafer using high contrast alignment marks is also described. Due to a difference in height of alignment marks and contact metal surrounding the alignment marks the alignment marks are transferred to the contour of the highly reflective electrode metal. A non reflective layer of bottom anti-reflection coating material is then used to provide high contrast at the location where the edges of the alignment marks are transferred to the highly reflective electrode metal.

摘要翻译： 描述了在用于图案化高反射电极金属层的集成电路晶片上形成高对比度对准标记的方法。 还描述了使用高对比度对准标记在集成电路晶片上图案化高反射金属层的方法。 由于对准标记的高度差和对准标记周围的接触金属的差异，对准标记被转印到高反射电极金属的轮廓上。 然后使用底部防反射涂层材料的非反射层来在对准标记的边缘被转印到高反射电极金属的位置处提供高对比度。

公开(公告)号：US06821896B1

公开(公告)日：2004-11-23

申请号：US09867563

申请日：2001-05-31

申请人： Tsu Shih

发明人： Tsu Shih

IPC分类号： H01L21302

CPC分类号： H01L21/76808

摘要： A method is provided for forming contact/via hole openings without the detrimental volcano effect that is normally encountered in forming damascene structures. It is disclosed that the hole openings are needed to be filled with a protective material, in the first place, so as to prevent any damage to the exposed surface at the bottom of the openings. However, the filling material must be chosen properly, for otherwise, the material can leave behind a scum-like residue which then can erupt like a volcano during the subsequent process steps, which in turn can lead to functionality as well as reliability problems. It is disclosed in the present invention that when i-line photoresist (i-line PR), or, spin-on organic oxide is used as the protective filler material, the volcano effect can be avoided, and a Cu dual damascene interconnect with low RC delay characteristics can be obtained.

摘要翻译： 提供了用于形成接触/通孔开口的方法，而没有在形成镶嵌结构时通常遇到的有害的火山效应。 公开了首先需要填充保护材料的孔口，以便防止在开口底部暴露的表面的任何损坏。 然而，必须正确选择填充材料，否则材料可能留下浮渣残留物，然后在随后的工艺步骤中可能像火山一样爆发，这反过来可能导致功能性和可靠性问题。 在本发明中公开了当使用i线光致抗蚀剂（i线PR）或旋涂有机氧化物作为保护性填充材料时，可以避免火山效应，并且Cu双镶嵌互连低 可以获得RC延迟特性。

公开(公告)号：US06682396B1

公开(公告)日：2004-01-27

申请号：US09546583

申请日：2000-04-11

申请人： Tsu Shih ,  Chen-Hua Yu

发明人： Tsu Shih ,  Chen-Hua Yu

IPC分类号： B24B4900

CPC分类号： B24B37/24 ,  B24B21/004 ,  B24B37/26

摘要： A linear polisher for polishing a substrate that always provides a fresh abrasive surface for polishing and a method for linear polishing a substrate are described. In the linear polisher, a length of a polishing pad is supported on a pair of rollers which are driven by a motor means for either intermittently or continuously advancing the pad during a polishing process. A vibration generator which is connected to the polishing pad through an adaptor provides lateral, or vibration in a transverse direction of the pad throughout the polishing process. The present invention novel linear polisher enables substantially constant removal rate to be achieved throughout the pad life of a polishing pad without deterioration such as that normally seen in a conventional rotary or linear CMP apparatus. Optionally, a rotatable substrate holder is utilized to further improve the polishing uniformity of the linear polishing apparatus.

摘要翻译： 描述了用于抛光总是提供用于抛光的新鲜研磨表面的基板的线性抛光机和用于线性抛光基板的方法。 在线性抛光机中，抛光垫的长度被支撑在一对辊上，该辊由用于在抛光过程中间歇地或连续地推进垫的马达装置驱动。 通过适配器连接到抛光垫的振动发生器在整个抛光过程中提供横向或在横向的振动。 本发明的新型线性抛光机能够在抛光垫的整个焊盘使用寿命期间实现基本上恒定的去除速率，而不会在常规的旋转或线性CMP设备中通常看到这样的劣化。 可选地，可旋转的基板保持器用于进一步改善线性抛光装置的抛光均匀性。