公开(公告)号：US20100013533A1

公开(公告)日：2010-01-21

申请号：US12390776

申请日：2009-02-23

申请人： Chen-Yi LEE ,  Jui-Yuan Yu ,  Juinn-Ting Chen

发明人： Chen-Yi LEE ,  Jui-Yuan Yu ,  Juinn-Ting Chen

IPC分类号： H03L7/06 ,  H03H11/26

CPC分类号： H03L7/0812 ,  H03H11/265 ,  H03K3/3565 ,  H03K5/133 ,  H03L7/0995 ,  H03L2207/50

摘要： A digital delay line includes a plurality of hysteresis-based delay cells electrically connected in series. These hystersis delay units in the hysteresis-based delay cells may be similar or different. All of the hysteresis delay units respectively have an inverter mode and a hesteresis mode. The delay and resolution of the hysteresis delay unit may be derived from the time difference in the inverter mode and hysteresis mode. Such a digital delay line applied to a digital phase locked loop may reduce consumption of area and power.

摘要翻译： 数字延迟线包括串联电连接的多个基于滞后的延迟单元。 基于滞后的延迟单元中的这些滞后延迟单元可以相似或不同。 所有滞后延迟单元分别具有逆变器模式和电渗模式。 迟滞延迟单元的延迟和分辨率可以从逆变器模式和滞后模式中的时间差导出。 应用于数字锁相环的这种数字延迟线可以减少面积和功率的消耗。

公开(公告)号：US07825713B2

公开(公告)日：2010-11-02

申请号：US12286765

申请日：2008-10-02

申请人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

发明人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

IPC分类号： H03H11/26

CPC分类号： G06F1/14

摘要： An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.

摘要翻译： 绝对时间延迟产生装置包括PVT（过程电压 - 温度）检测装置和延迟定时发生器。 PVT检测装置至少包括延迟模块和信号相位/频率控制模块。 延迟模块包括控制单元和参考单元。 控制单元与PVT的延迟属性的灵敏度不同于参考单元。 延迟模块比较原点信号分别通过控制单元和参考单元产生的相位或频率差，并产生延迟模块的延迟参数。 信号相位/频率控制模块接收并比较延迟参数以确定绝对时间延迟产生装置的环境PVT条件，以便控制和校正延迟定时发生器从而产生精确的绝对时间延迟。 在各种PVT影响下，绝对时间延迟产生装置能够产生精确的绝对时间信号。

公开(公告)号：US07924100B2

公开(公告)日：2011-04-12

申请号：US12180176

申请日：2008-07-25

申请人： Chen-Yi Lee ,  Jui-Yuan Yu

发明人： Chen-Yi Lee ,  Jui-Yuan Yu

IPC分类号： G01R23/00

CPC分类号： H03J7/04

摘要： A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.

摘要翻译： 通信设备使用本地时钟发生器从远程通信重新生成参考信号的载波频率。 特别地，闭环用于自校准本地脉冲，直到频率固定在固定的频率范围内。 一旦获得本地脉冲，解调器将使用本地脉冲来解调参考信号以产生数据信号。

公开(公告)号：US20090278617A1

公开(公告)日：2009-11-12

申请号：US12180176

申请日：2008-07-25

申请人： Chen-Yi Lee ,  Jui-Yuan Yu

发明人： Chen-Yi Lee ,  Jui-Yuan Yu

IPC分类号： G01R23/00 ,  H03J7/04

CPC分类号： H03J7/04

摘要： This invention discloses a crystal-less communication device and self-calibrated embedded virtual crystal clock generation method. In communication systems, the invention proposes a crystal-less scheme in the device for wireless or wired-line communications. The operation concepts are that the transmitter Device-1 provides Device-2 a reference signal, and Device-2 takes this signal to generate a local signal with the similar frequency that has limited frequency error compared with the one from Device-1. This invention is done via the circuit-design methodology, so it can be implemented from any kinds of circuit implementation processes, especially the CMOS process. As a result, the hardware can be designed in the way of highly integration and extremely low cost. Also, this can largely change and improve existing communications design architecture, hardware cost, and hardware area.

摘要翻译： 本发明公开了一种无晶体通信装置和自校准嵌入式虚拟晶体钟产生方法。 在通信系统中，本发明提出了一种无线或有线通信设备中的无晶体方案。 操作原理是发射机Device-1向Device-2提供参考信号，Device-2采用该信号产生与Device-1相比具有有限频率误差相似频率​​的本地信号。 本发明通过电路设计方法完成，因此可以通过任何种类的电路实现过程，特别是CMOS工艺实现。 因此，硬件可以以高集成度和极低成本的方式进行设计。 此外，这可以大大改变和改进现有的通信设计架构，硬件成本和硬件领域。

公开(公告)号：US20100013536A1

公开(公告)日：2010-01-21

申请号：US12286765

申请日：2008-10-02

申请人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

发明人： Chen-Yi Lee ,  Jui-Yuan Yu ,  Chien-Ying Yu ,  Juinn-Ting Chen

IPC分类号： H03H11/26

CPC分类号： G06F1/14

摘要： An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.