公开(公告)号：US20220297120A1

公开(公告)日：2022-09-22

申请号：US17695515

申请日：2022-03-15

Applicant: Chen-Yi LEE

Inventor： Chen-Yi LEE ,  Yun-Sheng CHAN

IPC: B01L3/00

Abstract: A microfluidic test system and method are provided. The microfluidic test system includes a control apparatus and a microfluidic chip. The control apparatus stores a test protocol of a biomedical test. The microfluidic chip includes a top plate and a microelectrode dot array having a plurality of microelectrode devices connected in series. The control apparatus provides a location-sensing signal to the microfluidic chip so that each microelectrode device detects a capacitance value between the top plate and the corresponding microfluidic electrode accordingly. The control apparatus provides a clock signal to the microfluidic chip so that each microelectrode device outputs the corresponding capacitance value accordingly. The control apparatus determines the size and location of a test sample within the microfluidic chip, generates a control signal according to the test protocol, the size, and the location, and provides the control signal to the microfluidic chip.

公开(公告)号：US08957477B2

公开(公告)日：2015-02-17

申请号：US13272994

申请日：2011-10-13

Applicant: Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

Inventor： Cheng-Hung Chang ,  Yu-Rung Hsu ,  Chen-Yi Lee ,  Shih-Ting Hung ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02617 ,  H01L29/1054 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fin. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Abstract translation: 形成半导体结构的方法包括提供复合衬底，该复合衬底包括在本体硅衬底上并邻接体硅衬底的体硅衬底和硅锗（SiGe）层。 对SiGe层进行第一次冷凝以形成冷凝的SiGe层，使得冷凝的SiGe层具有基本均匀的锗浓度。 蚀刻冷凝的SiGe层和体硅衬底的顶部以在硅片上形成包括硅翅片和冷凝的SiGe鳍的复合翅片。 该方法还包括氧化硅片的一部分; 并对冷凝的SiGe翅片进行第二冷凝。

公开(公告)号：US20130111304A1

公开(公告)日：2013-05-02

申请号：US13609829

申请日：2012-09-11

Applicant: Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

Inventor： Yi-Min Lin ,  Chih-Hsiang Hsu ,  Hsie-Chia Chang ,  Chen-Yi Lee

IPC: H03M13/07 ,  G06F11/10

CPC classification number: H03M13/152 ,  H03M13/1525 ,  H03M13/159 ,  H03M13/451 ,  H03M13/6502

Abstract: In a cyclic code decoding method, a decoder analyzes a received codeword to identify unreliable symbols in the codeword, and sets candidate syndrome patterns accordingly. Then, a syndrome calculator calculates evaluated syndrome values associated with one of the candidate syndrome patterns, and an error location polynomial (ELP) generator generates an ELP according to the syndrome values. An error correction device corrects the errors in the codeword according to theELP when a degree of the ELP is not more than a threshold value, and the syndrome calculator adjusts the syndrome values and the ELP generator generates another ELP according to the adjusted syndrome values when otherwise.

Abstract translation: 在循环码解码方法中，解码器分析接收的码字以识别码字中的不可靠符号，并相应地设置候选综合征模式。 然后，校正子计算器计算与候选校正子模式中的一个相关联的评估校正子值，并且错误位置多项式（ELP）生成器根据校正子值生成ELP。 当ELP的程度不大于阈值时，错误校正装置根据ELP校正码字中的错误，并且校正子计算器调整校正子值，并且ELP生成器根据校正的校正子值生成另一ELP， 除此以外。

公开(公告)号：US08263462B2

公开(公告)日：2012-09-11

申请号：US12347123

申请日：2008-12-31

Applicant: Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

Inventor： Shih-Ting Hung ,  Cheng-Hung Chang ,  Chen-Yi Lee ,  Chen-Nan Yeh ,  Chen-Hua Yu

IPC: H01L29/772

CPC classification number: H01L21/76202 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Abstract translation: 半导体结构包括具有第一部分和第二部分的半导体衬底。 第一Fin场效应晶体管（FinFET）形成在半导体衬底的第一部分上，其中第一FinFET包括具有第一鳍片高度的第一鳍片。 第二FinFET形成在半导体衬底的第二部分上，其中第二FinFET包括具有不同于第一鳍片高度的第二鳍片高度的第二鳍片。 第一翅片的顶表面基本上与第二翅片的顶表面平齐。 穿通止动件位于第一FinFET的下面并邻接，其中穿通止动件将第一鳍片与半导体衬底的第一部分隔离。

公开(公告)号：US20120159187A1

公开(公告)日：2012-06-21

申请号：US13034713

申请日：2011-02-25

Applicant: Po-Chun LIU ,  Hsie-Chia CHANG ,  Chen-Yi LEE

Inventor： Po-Chun LIU ,  Hsie-Chia CHANG ,  Chen-Yi LEE

IPC: G06F12/14

CPC classification number: G06F21/755

Abstract: An electronic device and a method for protecting against a differential power analysis attack are disclosed herein. The electronic device includes an encryption/decryption unit, a random number generator and a countermeasure circuit. The encryption/decryption unit can provide an enable signal when encrypting or decrypting more bits of data. The random number generator can generate random data. When receiving the enable signal, the countermeasure circuit can operate according to the bits of data and the random data.

Abstract translation: 本文公开了一种用于防止差分功率分析攻击的电子设备和方法。 电子设备包括加密/解密单元，随机数发生器和对策电路。 加密/解密单元可以在加密或解密更多数据位时提供使能信号。 随机数生成器可以生成随机数据。 当接收到使能信号时，对策电路可以根据数据位和随机数据进行操作。

公开(公告)号：US20110296281A1

公开(公告)日：2011-12-01

申请号：US12790875

申请日：2010-05-31

Applicant: Yi-Min LIN ,  Chi-Heng YANG ,  Hsie-Chia CHANG ,  Chen-Yi LEE

Inventor： Yi-Min LIN ,  Chi-Heng YANG ,  Hsie-Chia CHANG ,  Chen-Yi LEE

IPC: H03M13/07 ,  G06F11/10

CPC classification number: H03M13/1515 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1545 ,  H03M13/158 ,  H03M13/6513 ,  H03M13/6516 ,  H03M13/6561

Abstract: An apparatus and a method of processing cyclic codes are disclosed herein, where the apparatus includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.

Abstract translation: 本文公开了一种处理循环码的装置和方法，其中装置包括至少一个可重新配置模块和编码器控制器。 可重构模块包括多个线性反馈移位寄存器。 编码器控制器可以控制可重构模块将生成多项式归因于阶乘多项式。 在可重构模块中，线性反馈移位寄存器可分别注册多项因子多项式。

公开(公告)号：US20110273239A1

公开(公告)日：2011-11-10

申请号：US12805572

申请日：2010-08-06

Applicant: Chen-Yi Lee

Inventor： Chen-Yi Lee

IPC: H03B5/12 ,  H03K3/354

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1218 ,  H03B5/1221 ,  H03B5/124 ,  H03B2200/0008

Abstract: A dual positive-feedbacks voltage controlled oscillator includes an oscillation circuit and a cross coupled pair circuit. The oscillation circuit includes a first transistor, a second transistor, an inductor and a plurality of capacitors. The gates of the first and second transistors are opposite to each other and coupled to two points of the inductor. The inductor and the capacitors are formed as a LC tank. The cross coupled pair circuit includes a third transistor and a fourth transistor. The gates of the third and fourth transistors are cross coupled to two points of the inductor. Thereby, the gate of the third transistor is coupled to the gate of the second transistor; the gate of the fourth transistor is coupled to the gate of the first transistor; the drain of the third transistor is coupled to the source of the first transistor; and the drain of the fourth transistor is coupled to the source of the second transistor.

Abstract translation: 双正压电压振荡器包括振荡电路和交叉耦合对电路。 振荡电路包括第一晶体管，第二晶体管，电感器和多个电容器。 第一和第二晶体管的栅极彼此相对并耦合到电感器的两个点。 电感器和电容器形成为LC箱。 交叉耦合对电路包括第三晶体管和第四晶体管。 第三和第四晶体管的栅极交叉耦合到电感器的两个点。 由此，第三晶体管的栅极耦合到第二晶体管的栅极; 第四晶体管的栅极耦合到第一晶体管的栅极; 第三晶体管的漏极耦合到第一晶体管的源极; 并且第四晶体管的漏极耦合到第二晶体管的源极。

公开(公告)号：US07719442B2

公开(公告)日：2010-05-18

申请号：US12048101

申请日：2008-03-13

Applicant: Chih-Hao Liu ,  Chien-Ching Lin ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

Inventor： Chih-Hao Liu ,  Chien-Ching Lin ,  Chen-Yi Lee ,  Hsie-Chia Chang ,  Yarsun Hsu

IPC: H03M7/34

CPC classification number: H03M13/116 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/6561

Abstract: A multi-mode multi-parallelism data exchange method and the device thereof are proposed to apply to a check node operator or a bit node operator. The proposed method comprises the steps of: duplicating part or all of an original shift data as a duplicated shift data; combining the original shift data and the duplicated shift data to form a data block; and using a data block as the unit to shift this data block so as to conveniently retrieve shift data from the shifted data block. With a maximum z factor circuit and duplication of part of data, specifications of different shift sizes can be supported. The functions of shifters of several sizes can therefore be accomplished with the minimum complexity.

Abstract translation: 提出了一种多模式多并行数据交换方法及其装置，以应用于校验节点运算符或位节点运算符。 所提出的方法包括以下步骤：将原始移位数据的一部分或全部复制为复制移位数据; 组合原始移位数据和复制的移位数据以形成数据块; 并且使用数据块作为单元来移位该数据块，从而便于从移位的数据块检索移位数据。 通过最大的z因子电路和部分数据的重复，可以支持不同位移大小的规范。 因此可以以最小的复杂度来实现几种尺寸的移位器的功能。

公开(公告)号：US20100090769A1

公开(公告)日：2010-04-15

申请号：US12256316

申请日：2008-10-22

Applicant: Chen-yi Lee ,  Ching-che Chung

Inventor： Chen-yi Lee ,  Ching-che Chung

IPC: H03L7/099

CPC classification number: H03L7/093 ,  H03L2207/50

Abstract: A digital loop filter installed in an all-digital phase-locked loop (PLL) receives a digitally controlled oscillator (DCO) control code transmitted from a PLL controller in the all-digital PLL, and calculate an average value, such that the PLL controller can produce another DCO control code by the average value for controlling and adjusting an output signal of a digitally controlled oscillator (DCO) in the neighborhood of the average value to maintain compensating a phase/frequency difference with an input signal, so as to minimize the jitter effect of the input signal on the all-digital PLL, reduce the jitter effect of the output signal, and keep tracking and locking the frequency and the phase of the input signal.

Abstract translation: 安装在全数字锁相环（PLL）中的数字环路滤波器接收从全数字PLL中的PLL控制器发送的数控振荡器（DCO）控制码，并计算平均值，使得PLL控制器 可以通过用于控制和调整平均值附近的数控振荡器（DCO）的输出信号的平均值来产生另一个DCO控制代码，以维持用输入信号补偿相位/频率差，从而最小化 输入信号对全数字PLL的抖动效应，减少输出信号的抖动效应，并保持跟踪和锁定输入信号的频率和相位。

公开(公告)号：US20100017452A1

公开(公告)日：2010-01-21

申请号：US12325516

申请日：2008-12-01

Applicant: Chen-Yi LEE ,  Chen-Fong Hsiao ,  Yuan Chen

Inventor： Chen-Yi LEE ,  Chen-Fong Hsiao ,  Yuan Chen

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: For a large size FFT computation, this invention decomposes it into several smaller sizes FFT by decomposition equation and then transform the original index from one dimension into multi-dimension vector. By controlling the index vector, this invention could distribute the input data into different memory banks such that both the in-place policy for computation and the multi-bank memory for high-radix structure could be supported simultaneously without memory conflict. Besides, in order to keep memory conflict-free when the in-place policy is also adopted for I/O data, this invention reverses the decompose order of FFT to satisfy the vector reverse behavior. This invention can minimize the area and reduce the necessary clock rate effectively for general sized memory-based FFT processor design.

Abstract translation: 对于大尺寸FFT计算，本发明通过分解方程将其分解成若干较小尺寸的FFT，然后将原始索引从一维变换为多维向量。 通过控制索引向量，本发明可以将输入数据分配到不同的存储体中，使得可以在没有存储器冲突的情况下同时支持用于计算的就地策略和用于高基数结构的多存储存储器。 此外，为了在I / O数据也采用就地策略时保持内存无冲突的冲突，本发明反转FFT的分解顺序以满足向量反向行为。 本发明可以将面积最小化并有效地降低必要的时钟速率，用于一般尺寸的基于存储器的FFT处理器设计。