公开(公告)号：US08373272B2

公开(公告)日：2013-02-12

申请号：US12582690

申请日：2009-10-20

申请人： Chi Kang Liu ,  Talee Yu

发明人： Chi Kang Liu ,  Talee Yu

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L23/522 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01204 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrated circuit device comprising an improved bonding pad structure. The device has a semiconductor substrate. A plurality of active MOS devices are formed on the semiconductor substrate. The device has an interlayer dielectric layer overlying the plurality of active MOS devices and at least one single metal bonding pad formed on the interlayer dielectric layer and directly over at least one of the active devices. At least four edge regions are formed on a square shape of the at least one single metal bonding pad. An angled cut region is formed on each of the four edge regions. The device has a buffer metal layer free region located between the plurality of active MOS devices and the at least one single metal bonding pad. The buffer metal layer free region does not have a buffer metal layer in the interlayer dielectric layer.

摘要翻译： 一种集成电路器件，包括改进的焊盘结构。 该器件具有半导体衬底。 在半导体衬底上形成多个有源MOS器件。 该器件具有覆盖多个有源MOS器件的层间介质层和形成在层间介质层上并直接位于至少一个有源器件上的至少一个单一金属焊盘。 至少四个边缘区域形成在至少一个单个金属接合焊盘的正方形上。 在四个边缘区域中的每一个上形成有角度切割区域。 该器件具有位于多个有源MOS器件和至少一个单个金属焊盘之间的缓冲金属层自由区域。 缓冲金属层自由区在层间介质层中不具有缓冲金属层。

公开(公告)号：US20100213551A1

公开(公告)日：2010-08-26

申请号：US12702984

申请日：2010-02-09

申请人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

发明人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

IPC分类号： H01L27/105 ,  H01L23/525

CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An e-fuse and an e-fuse control circuit are provided. The e-fuse includes a polysilicon layer and a metal silicide layer stacked on the polysilicon layer. The e-fuse operates in an open state when the silicide layer is broken by burning while one portion of the polysilicon layer is exposed.

摘要翻译： 提供电子熔丝和电熔丝控制电路。 电熔丝包括堆叠在多晶硅层上的多晶硅层和金属硅化物层。 当硅化物层通过燃烧而破坏时，e熔丝工作在打开状态，同时暴露多晶硅层的一部分。

公开(公告)号：US20100027172A1

公开(公告)日：2010-02-04

申请号：US12483195

申请日：2009-06-11

申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

IPC分类号： H02H9/04 ,  H01L29/739 ,  H01L21/331

CPC分类号： H01L27/0259 ,  H01L29/7835

摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

摘要翻译： 用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。 井区的特征在于第一深度。 该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。 发射极区域的特征在于第二导电类型。 第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。 第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

公开(公告)号：US09235297B2

公开(公告)日：2016-01-12

申请号：US12874273

申请日：2010-09-02

申请人： Chi Kang Liu

发明人： Chi Kang Liu

IPC分类号： G06F3/044 ,  G06F3/041 ,  G02F1/1333 ,  G09G3/36

CPC分类号： G06F3/044 ,  G02F1/13338 ,  G06F3/0412 ,  G09G3/3655

摘要： A capacitive touch screen sensing apparatus is provided. The apparatus includes a protecting layer; a sensing layer under the protecting layer for sensing a touch to generate a position signal; and a DC common voltage signal layer electrically connected with a DC voltage for shielding against signal interferences.

摘要翻译： 提供一种电容式触摸屏感测装置。 该装置包括保护层; 保护层下面的感测层，用于感测触摸以产生位置信号; 以及与用于屏蔽信号干扰的直流电压电连接的直流公共电压信号层。

公开(公告)号：US08638304B2

公开(公告)日：2014-01-28

申请号：US12838567

申请日：2010-07-19

申请人： Chi Kang Liu ,  Chin-Wei Lin

发明人： Chi Kang Liu ,  Chin-Wei Lin

IPC分类号： G06F3/041

CPC分类号： G06F3/0416

摘要： A touch screen includes an LCD panel; a display controller for processing a video signal to generate a panel control signal and a sensing control signal, with the panel control signal controlling the LCD panel so that the LCD panel displays images according to the panel control signal; a touch panel, for generating the sensing signal in response to a touch; and a sensing circuit, coupled to the touch panel and the display controller, for receiving the sensing signal and the sensing control signal to generate a position signal with reference to the sensing control signal.

摘要翻译： 触摸屏包括LCD面板; 用于处理视频信号以产生面板控制信号和感测控制信号的显示控制器，面板控制信号控制LCD面板，使得LCD面板根据面板控制信号显示图像; 触摸面板，用于响应于触摸而产生感测信号; 以及耦合到触摸面板和显示控制器的感测电路，用于接收感测信号和感测控制信号，以参考感测控制信号产生位置信号。

公开(公告)号：US08525822B2

公开(公告)日：2013-09-03

申请号：US12769901

申请日：2010-04-29

申请人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

发明人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

IPC分类号： G06F3/038 ,  G09G5/00

CPC分类号： G09G3/3688 ,  G09G2330/06

摘要： A driving circuit on a liquid crystal display (LCD) panel and associated control method is provided. The LCD panel connected to a display control circuit via a flexible print circuit (FPC) includes a master source driver, for inputting a digital image signal in compliance with a first electrical specification via an FPC board and converting the digital image signal to a gate driving signal and a slave source driving signal, which are in compliance with a second electrical specification; a gate driver, for receiving the gate driving signal in compliance with the second electrical specification; and a slave source driver, for receiving the slave source driving signal in compliance with the second electrical specification. The master source driver, the slave source driver and the gate driver drive a thin-film transistor (TFT) on the LCD panel.

摘要翻译： 提供了液晶显示器（LCD）面板上的驱动电路和相关的控制方法。 通过柔性印刷电路（FPC）连接到显示控制电路的LCD面板包括主源驱动器，用于经由FPC板输入符合第一电气规格的数字图像信号，并将数字图像信号转换为栅极驱动 信号和从源驱动信号，其符合第二电气规范; 门驱动器，用于接收符合第二电气规范的门驱动信号; 和从源驱动器，用于接收符合第二电气规范的从源驱动信号。 主源驱动器，从源驱动器和栅极驱动器驱动LCD面板上的薄膜晶体管（TFT）。

公开(公告)号：US08368186B2

公开(公告)日：2013-02-05

申请号：US13076269

申请日：2011-03-30

申请人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

发明人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

IPC分类号： H01L23/552

CPC分类号： H01L27/0255 ,  H01L24/05 ,  H01L2924/12036 ,  H01L2924/13034 ,  H01L2924/14 ,  H01L2924/00

摘要： An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

摘要翻译： ESD器件包括设置在半导体衬底中的第一和第二阱区。 第一阱区域包括以预定长度间隔开的多个N阱。 重掺杂的P +区域和重掺杂的N +区域设置在每个N个阱中。 重掺杂N +区域耦合到Vdd，并且N阱中的重掺杂P +区域电耦合到相邻N阱中的重掺杂N +区域。 第二井区域包括邻接N井的P井。 在P阱中设置重掺杂P +区和重掺杂N +区。 P阱中的重掺杂N +区域与I / O电路共同地电耦合到相邻N阱的重掺杂P +区域，并且重掺杂P +区域耦合到Vss。

公开(公告)号：US20120074539A1

公开(公告)日：2012-03-29

申请号：US13076269

申请日：2011-03-30

申请人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

发明人： Ta Lee Yu ,  Chi Kang Liu ,  Jing Liu

IPC分类号： H01L23/552

CPC分类号： H01L27/0255 ,  H01L24/05 ,  H01L2924/12036 ,  H01L2924/13034 ,  H01L2924/14 ,  H01L2924/00

摘要： An ESD device includes a first and second well regions disposed in a semiconductor substrate. The first well region comprises a plurality of N wells spaced at a predetermined length. A heavily doped P+ region and a heavily doped N+ region are disposed in each of the N wells. The heavily doped N+ region is coupled to Vdd and a heavily doped P+ region in an N well is electrically coupled to the heavily doped N+ region in an adjacent N well. The second well region comprises a P well abutting an N well. A heavily doped P+ region and a heavily doped N+ region are disposed in the P well. The heavily doped N+ region in the P well is electrically coupled to the heavily doped P+ region of the adjacent N well in common with an I/O circuit, and the heavily doped P+ region is coupled to Vss.

摘要翻译： ESD器件包括设置在半导体衬底中的第一和第二阱区。 第一阱区域包括以预定长度间隔开的多个N阱。 重掺杂的P +区域和重掺杂的N +区域设置在每个N个阱中。 重掺杂N +区域耦合到Vdd，并且N阱中的重掺杂P +区域电耦合到相邻N阱中的重掺杂N +区域。 第二井区域包括邻接N井的P井。 在P阱中设置重掺杂P +区和重掺杂N +区。 P阱中的重掺杂N +区域与I / O电路共同地电耦合到相邻N阱的重掺杂P +区域，并且重掺杂P +区域耦合到Vss。

公开(公告)号：US08891213B2

公开(公告)日：2014-11-18

申请号：US13244292

申请日：2011-09-24

申请人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

发明人： Chi Kang Liu ,  Ta Lee Yu ,  Quan Li

IPC分类号： H02H9/00 ,  H01L27/02 ,  H01L29/78 ,  H02H3/22 ,  H02H3/02 ,  H02H3/08

CPC分类号： H01L27/0259 ,  H01L29/7835

摘要： A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

摘要翻译： 用于ESD保护的半导体器件包括形成在衬底内的第一导电类型的半导体衬底和第二导电类型的阱区。 井区的特征在于第一深度。 该器件包括MOS晶体管，第一双极晶体管和第二双极晶体管。 MOS晶体管包括在阱区内的第二深度的第一轻掺杂漏极（LDD）区域，以及在第一LDD区域内的漏极区域和发射极区域。 发射极区域的特征在于第二导电类型。 第一双极晶体管与发射极区域，第一LDD区域和阱区域相关联，并且其特征在于第一触发电压。 第二双极晶体管与第一LDD区，阱区和衬底相关联，并且其特征在于第二触发电压。

公开(公告)号：US08258598B2

公开(公告)日：2012-09-04

申请号：US12702984

申请日：2010-02-09

申请人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

发明人： Chi Kang Liu ,  Chin-Wei Lin ,  Min-Nan Hsieh

IPC分类号： H01L29/00

CPC分类号： H01L27/0629 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An e-fuse and an e-fuse control circuit are provided. The e-fuse includes a polysilicon layer and a metal silicide layer stacked on the polysilicon layer. The e-fuse operates in an open state when the silicide layer is broken by burning while one portion of the polysilicon layer is exposed.

摘要翻译： 提供电子熔丝和电熔丝控制电路。 电熔丝包括堆叠在多晶硅层上的多晶硅层和金属硅化物层。 当硅化物层通过燃烧而破坏时，e熔丝工作在打开状态，同时暴露多晶硅层的一部分。