公开(公告)号：US20150370705A1

公开(公告)日：2015-12-24

申请号：US14837857

申请日：2015-08-27

申请人： Chi Weon YOON ,  Dong Hyuk CHAE ,  Sang-Wan NAM ,  Jung-Yun YUN

发明人： Chi Weon YOON ,  Dong Hyuk CHAE ,  Sang-Wan NAM ,  Jung-Yun YUN

IPC分类号： G06F12/06 ,  G06F3/06

CPC分类号： G06F12/0646 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F2212/2022 ,  G11C5/025 ,  G11C8/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483

摘要： At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

摘要翻译： 至少一个地址调度方法包括选择第一位线，选择连接到第一位线的第一串，在第一串中的每个多电平单元的N页上从底部字线到顶部执行地址调度 字线，并且在完成第一串中的所有字线上的地址调度之后，以与对第一字符串执行的相同的方式依次执行第二至第K个字符串的地址调度，其中“k”为2或 自然数大于2。

公开(公告)号：US20110205817A1

公开(公告)日：2011-08-25

申请号：US13027439

申请日：2011-02-15

申请人： Sang Yong YOON ,  Dong Hyuk CHAE ,  Bo Geun KIM

发明人： Sang Yong YOON ,  Dong Hyuk CHAE ,  Bo Geun KIM

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5648

摘要： A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy.

摘要翻译： 存储器系统包括多位存储器件和控制多位存储器件的存储器控​​制器。 存储器系统确定所请求的程序操作是随机程序操作还是顺序程序操作。 在所请求的程序操作是随机程序操作的情况下，存储器控制器控制多位存储器件根据精细程序关闭策略或精细程序打开策略执行操作。

公开(公告)号：US20080276150A1

公开(公告)日：2008-11-06

申请号：US11905734

申请日：2007-10-03

申请人： Jun Jin KONG ,  Seung-Hwan SONG ,  Dong Hyuk CHAE ,  Kyoung Lae CHO ,  Seung Jae LEE ,  Nam Phil JO ,  Sung Chung PARK ,  Dong Ku KANG

发明人： Jun Jin KONG ,  Seung-Hwan SONG ,  Dong Hyuk CHAE ,  Kyoung Lae CHO ,  Seung Jae LEE ,  Nam Phil JO ,  Sung Chung PARK ,  Dong Ku KANG

IPC分类号： G06F11/08

CPC分类号： G06F11/1072

摘要： An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.

摘要翻译： 应用于多电平单元（MLC）方法的存储器的错误控制代码（ECC）装置可以包括：旁路控制信号发生器，其生成旁路控制信号; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。 另外或在替代方案中，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。 还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

公开(公告)号：US20090070656A1

公开(公告)日：2009-03-12

申请号：US12191458

申请日：2008-08-14

申请人： Nam Phil JO ,  Jun Jin KONG ,  Chan Ho YOON ,  Dong Hyuk CHAE ,  Kyoung Lae CHO

发明人： Nam Phil JO ,  Jun Jin KONG ,  Chan Ho YOON ,  Dong Hyuk CHAE ,  Kyoung Lae CHO

IPC分类号： G11C29/04 ,  G06F11/07

CPC分类号： G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411

摘要： A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

摘要翻译： 存储器系统包括：包括纠错解码器的存储器控​​制器。 纠错解码器包括：解复用器，适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器 以及多路复用器，其适于多路复用第一组数据和第二组数据，并将复用的数据提供给误差校正器。 当误差校正器校正第一组数据中的错误时，误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。

公开(公告)号：US20080137443A1

公开(公告)日：2008-06-12

申请号：US11941101

申请日：2007-11-16

申请人： Dong Hyuk CHAE ,  Young Ho LIM

发明人： Dong Hyuk CHAE ,  Young Ho LIM

IPC分类号： G11C16/26

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

摘要： A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the man data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

摘要翻译： 提供一种包括存储器阵列，页缓冲器和行解码器的非易失性半导体存储器件。 存储器阵列包括多个非易失性存储器单元，位线和字线，并且行解码器被驱动以控制存储器阵列的字线。 页缓冲器电连接到位线，并包括主数据锁存器和子数据锁存器。 根据子数据锁存器的逻辑状态禁止翻转人数据锁存器的页缓冲器还包括主锁存块，子锁存块和锁存控制块。 主锁存块驱动主数据锁存器，并通过位线将主数据锁存器的逻辑状态映射到相应存储器单元的阈值电压。 子锁存块驱动子数据锁存器，其中子数据锁存器根据位线的电压电平翻转。 锁存控制块根据位线的电压电平有选择地翻转主数据锁存器，根据子数据锁存器的逻辑状态，禁止锁存器控制块。