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    N-well and N+ buried layer isolation by auto doping to reduce chip size
    2.
    发明授权
    N-well and N+ buried layer isolation by auto doping to reduce chip size 有权
    N阱和N +埋层隔离通过自动掺杂减少芯片尺寸

    公开(公告)号：US07436043B2

    公开(公告)日：2008-10-14

    申请号：US11019753

    申请日：2004-12-21

    申请人： Tzu-Chiang Sung ,  Chih Po Huang ,  Rann Shyan Yeh ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Chung-I Chen

    发明人： Tzu-Chiang Sung ,  Chih Po Huang ,  Rann Shyan Yeh ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Chung-I Chen

    IPC分类号： H01L21/74

    CPC分类号： H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928

    摘要： A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.

    摘要翻译： 半导体器件包括多个以不同电位偏置的低电压N阱（LVNW）区域，并且通过公共N + +掩埋层（NBL）和至少一个高压N阱（ HVNW）区域。 LVNW区域通过公共的P + SUPER +掩埋层（PBL）耦合到公共的下部NBL。 形成可用于半导体器件的衬底的方法包括在负偏压的P型半导体衬底的指定低电压区域中形成NBL，在NBL区的一部分中通过注入P型杂质离子形成PBL 铟化合到PBL中，并且通过使P型杂质离子扩散到P型外延层中使得PBL延伸到NBL中的条件在PBL上生长P型外延层。 在P型外延层中也形成低压P阱区，并与PBL接触。

    N-well and N+ buried layer isolation by auto doping to reduce chip size
    4.
    发明申请
    N-well and N+ buried layer isolation by auto doping to reduce chip size 有权
    N阱和N +埋层隔离通过自动掺杂减少芯片尺寸

    公开(公告)号：US20060133189A1

    公开(公告)日：2006-06-22

    申请号：US11019753

    申请日：2004-12-21

    申请人： Tzu-Chiang Sung ,  Chih Huang ,  Rann Shyan Yeh ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Chung-I Chen

    发明人： Tzu-Chiang Sung ,  Chih Huang ,  Rann Shyan Yeh ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Chung-I Chen

    IPC分类号： G11C7/10

    CPC分类号： H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928

    摘要： A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.

    摘要翻译： 半导体器件包括多个以不同电位偏置的低电压N阱（LVNW）区域，并且通过公共N + +掩埋层（NBL）和至少一个高压N阱（ HVNW）区域。 LVNW区域通过公共的P + SUPER +掩埋层（PBL）耦合到公共的下部NBL。 形成可用于半导体器件的衬底的方法包括在负偏压的P型半导体衬底的指定低电压区域中形成NBL，在NBL区的一部分中通过注入P型杂质离子形成PBL 铟化合到PBL中，并且通过使P型杂质离子扩散到P型外延层中使得PBL延伸到NBL中的条件在PBL上生长P型外延层。 在P型外延层中也形成低压P阱区，并与PBL接触。

    Semiconductor structure for isolating integrated circuits of various operating voltages
    5.
    发明授权
    Semiconductor structure for isolating integrated circuits of various operating voltages 有权
    用于隔离各种工作电压的集成电路的半导体结构

    公开(公告)号：US07498653B2

    公开(公告)日：2009-03-03

    申请号：US11273228

    申请日：2005-11-12

    申请人： Chia-Wei Liu ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

    发明人： Chia-Wei Liu ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

    IPC分类号： H01L29/00

    CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L27/088

    摘要： A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.

    摘要翻译： 用于隔离各种工作电压的第一电路和第二电路的半导体结构包括围绕半导体衬底上的第一和第二电路的第一隔离环。 在第一和第二电路下连续延伸的掩埋层形成在半导体衬底上，其中掩埋层与第一隔离环接合，用于将第一和第二电路与半导体衬底的背面偏置隔离。 离子增强隔离层介于掩埋层和形成有第一和第二电路的器件的阱区之间，其中离子增强隔离层掺杂了与掩埋层不同的极性类型的杂质。

    Self-aligned method for defining a semiconductor gate oxide in high voltage device area
    6.
    发明授权
    Self-aligned method for defining a semiconductor gate oxide in high voltage device area 有权
    用于在高电压器件区域中限定半导体栅极氧化物的自对准方法

    公开(公告)号：US07253114B2

    公开(公告)日：2007-08-07

    申请号：US11082514

    申请日：2005-03-16

    申请人： Chien-Mao Chen ,  Jun Xiu Liu ,  Cuker Huang ,  Chi-Hsuen Chang

    发明人： Chien-Mao Chen ,  Jun Xiu Liu ,  Cuker Huang ,  Chi-Hsuen Chang

    IPC分类号： H01L21/302

    CPC分类号： H01L21/823481 ,  H01L21/823462 ,  Y10S438/942

    摘要： A method is provided for forming at least three devices with different gate oxide thicknesses and different associated operating voltages, in the same integrated circuit device. The method includes forming a plurality of gate oxides with different thicknesses in high voltage and low voltage areas in the same integrated circuit device. A dry etching operation is used to remove the relatively thick gate oxide from the high voltage area using photoresist masking of the low voltage area and a hard mask in the high voltage area, to mask the gate oxide films. A wet etching procedure is then used to remove the gate oxide film from the low voltage areas. The hard mask may be formed over a polysilicon structure.

    摘要翻译： 在相同的集成电路器件中提供了一种用于形成具有不同栅极氧化物厚度和不同相关工作电压的至少三个器件的方法。 该方法包括在同一集成电路器件中在高电压和低电压区域形成具有不同厚度的多个栅极氧化物。 使用干蚀刻操作，使用低电压区域的光掩模和高电压区域中的硬掩模从高电压区域去除相对厚的栅极氧化物，以掩蔽栅极氧化物膜。 然后使用湿蚀刻步骤从低电压区域去除栅氧化膜。 硬掩模可以形成在多晶硅结构上。