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    N-well and N+ buried layer isolation by auto doping to reduce chip size
    1.
    发明申请
    N-well and N+ buried layer isolation by auto doping to reduce chip size 有权
    N阱和N +埋层隔离通过自动掺杂减少芯片尺寸

    公开(公告)号：US20060133189A1

    公开(公告)日：2006-06-22

    申请号：US11019753

    申请日：2004-12-21

    申请人： Tzu-Chiang Sung ,  Chih Huang ,  Rann Shyan Yeh ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Chung-I Chen

    发明人： Tzu-Chiang Sung ,  Chih Huang ,  Rann Shyan Yeh ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Chung-I Chen

    IPC分类号： G11C7/10

    CPC分类号： H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928

    摘要： A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.

    摘要翻译： 半导体器件包括多个以不同电位偏置的低电压N阱（LVNW）区域，并且通过公共N + +掩埋层（NBL）和至少一个高压N阱（ HVNW）区域。 LVNW区域通过公共的P + SUPER +掩埋层（PBL）耦合到公共的下部NBL。 形成可用于半导体器件的衬底的方法包括在负偏压的P型半导体衬底的指定低电压区域中形成NBL，在NBL区的一部分中通过注入P型杂质离子形成PBL 铟化合到PBL中，并且通过使P型杂质离子扩散到P型外延层中使得PBL延伸到NBL中的条件在PBL上生长P型外延层。 在P型外延层中也形成低压P阱区，并与PBL接触。

    Semiconductor structure for isolating integrated circuits of various operating voltages
    3.
    发明授权
    Semiconductor structure for isolating integrated circuits of various operating voltages 有权
    用于隔离各种工作电压的集成电路的半导体结构

    公开(公告)号：US07498653B2

    公开(公告)日：2009-03-03

    申请号：US11273228

    申请日：2005-11-12

    申请人： Chia-Wei Liu ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

    发明人： Chia-Wei Liu ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

    IPC分类号： H01L29/00

    CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L27/088

    摘要： A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.

    摘要翻译： 用于隔离各种工作电压的第一电路和第二电路的半导体结构包括围绕半导体衬底上的第一和第二电路的第一隔离环。 在第一和第二电路下连续延伸的掩埋层形成在半导体衬底上，其中掩埋层与第一隔离环接合，用于将第一和第二电路与半导体衬底的背面偏置隔离。 离子增强隔离层介于掩埋层和形成有第一和第二电路的器件的阱区之间，其中离子增强隔离层掺杂了与掩埋层不同的极性类型的杂质。

    N-well and N+ buried layer isolation by auto doping to reduce chip size
    4.
    发明授权
    N-well and N+ buried layer isolation by auto doping to reduce chip size 有权
    N阱和N +埋层隔离通过自动掺杂减少芯片尺寸

    公开(公告)号：US07436043B2

    公开(公告)日：2008-10-14

    申请号：US11019753

    申请日：2004-12-21

    申请人： Tzu-Chiang Sung ,  Chih Po Huang ,  Rann Shyan Yeh ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Chung-I Chen

    发明人： Tzu-Chiang Sung ,  Chih Po Huang ,  Rann Shyan Yeh ,  Jun Xiu Liu ,  Chi-Hsuen Chang ,  Chung-I Chen

    IPC分类号： H01L21/74

    CPC分类号： H01L21/761 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928

    摘要： A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.

    摘要翻译： 半导体器件包括多个以不同电位偏置的低电压N阱（LVNW）区域，并且通过公共N + +掩埋层（NBL）和至少一个高压N阱（ HVNW）区域。 LVNW区域通过公共的P + SUPER +掩埋层（PBL）耦合到公共的下部NBL。 形成可用于半导体器件的衬底的方法包括在负偏压的P型半导体衬底的指定低电压区域中形成NBL，在NBL区的一部分中通过注入P型杂质离子形成PBL 铟化合到PBL中，并且通过使P型杂质离子扩散到P型外延层中使得PBL延伸到NBL中的条件在PBL上生长P型外延层。 在P型外延层中也形成低压P阱区，并与PBL接触。

    Semiconductor structure for isolating integrated circuits of various operation voltages
    6.
    发明申请
    Semiconductor structure for isolating integrated circuits of various operation voltages 有权
    用于隔离各种工作电压的集成电路的半导体结构

    公开(公告)号：US20060113571A1

    公开(公告)日：2006-06-01

    申请号：US11136810

    申请日：2005-05-24

    申请人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Huang

    发明人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Huang

    IPC分类号： H01L29/768

    CPC分类号： H01L21/761 ,  H01L21/76232 ,  H01L27/088 ,  H01L27/0921

    摘要： A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.

    摘要翻译： 半导体结构包括设置在半导体衬底上的隔离环，围绕第一和第二电路区域。 掩埋隔离层在半导体衬底中连续延伸穿过第一电路区域和第二电路区域。 掩埋隔离层与隔离环接合，从而将第一和第二电路区域与半导体衬底的背面偏置隔离。 离子增强隔离层将第一电路区域中的第一阱和第二电路区域中的第二阱与隔离环和掩埋隔离层分离，从而防止电路区域的阱和掩埋隔离层之间的穿通 。

    Semiconductor structure for isolating integrated circuits of various operating voltages
    8.
    发明申请
    Semiconductor structure for isolating integrated circuits of various operating voltages 有权
    用于隔离各种工作电压的集成电路的半导体结构

    公开(公告)号：US20070235831A1

    公开(公告)日：2007-10-11

    申请号：US11273228

    申请日：2005-11-12

    申请人： Chia-Wei Liu ,  Jun Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

    发明人： Chia-Wei Liu ,  Jun Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Rann-Shyan Yeh

    IPC分类号： H01L29/00 ,  H01L21/76

    CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L27/088

    摘要： A semiconductor structure for isolating a first circuit and a second circuit of various operating voltages includes a first isolation ring surrounding the first and second circuits on a semiconductor substrate. A buried layer continuously extending underneath the first and second circuits is formed on the semiconductor substrate, wherein the buried layer interfaces with the first isolation ring for isolating the first and second circuits from a backside bias of the semiconductor substrate. An ion enhanced isolation layer is interposed between the buried layer and well regions on which devices of the first and second circuits are formed, wherein the ion enhanced isolation layer is doped with impurities of a polarity type different from that of the buried layer.

    摘要翻译： 用于隔离各种工作电压的第一电路和第二电路的半导体结构包括围绕半导体衬底上的第一和第二电路的第一隔离环。 在第一和第二电路下连续延伸的掩埋层形成在半导体衬底上，其中掩埋层与第一隔离环接合，用于将第一和第二电路与半导体衬底的背面偏置隔离。 离子增强隔离层介于掩埋层和形成有第一和第二电路的器件的阱区之间，其中离子增强隔离层掺杂了与掩埋层不同的极性类型的杂质。

    Semiconductor structure for isolating integrated circuits of various operation voltages
    9.
    发明授权
    Semiconductor structure for isolating integrated circuits of various operation voltages 有权
    用于隔离各种工作电压的集成电路的半导体结构

    公开(公告)号：US07196392B2

    公开(公告)日：2007-03-27

    申请号：US11136810

    申请日：2005-05-24

    申请人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Po Huang

    发明人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Po Huang

    IPC分类号： H01L29/00

    CPC分类号： H01L21/761 ,  H01L21/76232 ,  H01L27/088 ,  H01L27/0921

    摘要： A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.

    摘要翻译： 半导体结构包括设置在半导体衬底上的隔离环，围绕第一和第二电路区域。 掩埋隔离层在半导体衬底中连续延伸穿过第一电路区域和第二电路区域。 掩埋隔离层与隔离环接合，从而将第一和第二电路区域与半导体衬底的背面偏置隔离。 离子增强隔离层将第一电路区域中的第一阱和第二电路区域中的第二阱与隔离环和掩埋隔离层分离，从而防止电路区域的阱和掩埋隔离层之间的穿通 。

    Method and apparatus for a semiconductor device having low and high voltage transistors
    10.
    发明申请
    Method and apparatus for a semiconductor device having low and high voltage transistors 有权
    具有低和高压晶体管的半导体器件的方法和装置

    公开(公告)号：US20060006462A1

    公开(公告)日：2006-01-12

    申请号：US11122635

    申请日：2005-05-05

    申请人： Chi-Hsuen Chang ,  Jun Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Huang ,  Rann Yeh

    发明人： Chi-Hsuen Chang ,  Jun Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Huang ,  Rann Yeh

    IPC分类号： H01L29/76

    CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7391 ,  H01L29/7816

    摘要： Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.

    摘要翻译： 描述了包括高压MOS晶体管的半导体器件的方法和装置。 衬底设置有彼此分离的低电压和高电压区域。 形成包含绝缘体的隔离区，包括形成在高电压区域内的所述阱内的至少一个。 从高电压装置区域中的有源区域到隔离区域的转变角度大于预定角度，在一些实施例中，它与垂直方向大于40度。 在一些实施例中，使用浅沟槽隔离技术形成隔离区域。 在替代实施例中，使用通过硅技术的局部氧化形成的场氧化物形成隔离区。