公开(公告)号：US07205630B2

公开(公告)日：2007-04-17

申请号：US11122635

申请日：2005-05-05

申请人： Chi-Hsuen Chang ,  Jun Xiu Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Po Huang ,  Rann Shyan Yeh

发明人： Chi-Hsuen Chang ,  Jun Xiu Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Po Huang ,  Rann Shyan Yeh

IPC分类号： H01L29/00

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7391 ,  H01L29/7816

摘要： Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.

摘要翻译： 描述了包括高压MOS晶体管的半导体器件的方法和装置。 衬底设置有彼此分离的低电压和高电压区域。 形成包含绝缘体的隔离区，包括形成在高电压区域内的所述阱内的至少一个。 从高电压装置区域中的有源区域到隔离区域的转变角度大于预定角度，在一些实施例中，它与垂直方向大于40度。 在一些实施例中，使用浅沟槽隔离技术形成隔离区域。 在替代实施例中，使用通过硅技术的局部氧化形成的场氧化物形成隔离区。

公开(公告)号：US20060006462A1

公开(公告)日：2006-01-12

申请号：US11122635

申请日：2005-05-05

申请人： Chi-Hsuen Chang ,  Jun Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Huang ,  Rann Yeh

发明人： Chi-Hsuen Chang ,  Jun Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Huang ,  Rann Yeh

IPC分类号： H01L29/76

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7391 ,  H01L29/7816

摘要： Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.

摘要翻译： 描述了包括高压MOS晶体管的半导体器件的方法和装置。 衬底设置有彼此分离的低电压和高电压区域。 形成包含绝缘体的隔离区，包括形成在高电压区域内的所述阱内的至少一个。 从高电压装置区域中的有源区域到隔离区域的转变角度大于预定角度，在一些实施例中，它与垂直方向大于40度。 在一些实施例中，使用浅沟槽隔离技术形成隔离区域。 在替代实施例中，使用通过硅技术的局部氧化形成的场氧化物形成隔离区。

公开(公告)号：US09257421B2

公开(公告)日：2016-02-09

申请号：US14728189

申请日：2015-06-02

申请人： Tsung-Yi Huang ,  Kuo-Hsuan Lo ,  Wu-Te Weng

发明人： Tsung-Yi Huang ,  Kuo-Hsuan Lo ,  Wu-Te Weng

IPC分类号： H01L29/66 ,  H01L27/02 ,  H01L29/866 ,  H01L21/762

CPC分类号： H01L27/0255 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/66106 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/866

摘要： The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer.

摘要翻译： 本发明公开了一种瞬态电压抑制（TVS）装置及其制造方法。 TVS器件限制其两个端子之间的电压降不超过钳位电压。 TVS器件形成在堆叠衬底中，该衬底包括依次层叠的半导体衬底，P型第一外延层和第二外延层。 在TVS器件中，第一PN二极管串联连接到齐纳二极管，其中串联电路由第一浅沟槽隔离（STI）区域包围; 并且第二PN二极管与串联电路并联连接，其中第二PN二极管被第二STI区域包围。 第一STI区域和第​​二STI区域都从上表面延伸到第二外延层，而不是延伸到第一外延层。

公开(公告)号：US09245746B2

公开(公告)日：2016-01-26

申请号：US14048971

申请日：2013-10-08

申请人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

发明人： Hung-Der Su ,  Chien-Wei Chiu ,  Tsung-Yi Huang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/12

CPC分类号： H01L29/205 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/02664 ,  H01L21/30612 ,  H01L29/12 ,  H01L29/2003 ,  H01L29/7845 ,  H01L29/7849

摘要： The present invention discloses a semiconductor composite film with a heterojunction and a manufacturing method thereof. The semiconductor composite film includes: a semiconductor substrate; and a semiconductor epitaxial layer, which is formed on the semiconductor substrate, and it has a first surface and a second surface opposite to each other, wherein the heterojunction is formed between the first surface and the semiconductor substrate, and wherein the semiconductor epitaxial layer further includes at least one recess, which is formed by etching the semiconductor epitaxial layer from the second surface toward the first surface. The recess is for mitigating a strain in the semiconductor composite film.

摘要翻译： 本发明公开了一种具有异质结的半导体复合膜及其制造方法。 半导体复合膜包括：半导体衬底; 以及半导体外延层，其形成在所述半导体基板上，并且具有彼此相对的第一表面和第二表面，其中所述异质结形成在所述第一表面和所述半导体基板之间，并且其中所述半导体外延层进一步 包括通过从第二表面朝向第一表面蚀刻半导体外延层而形成的至少一个凹部。 该凹槽用于减轻半导体复合膜中的应变。

公开(公告)号：US20150364460A1

公开(公告)日：2015-12-17

申请号：US14728189

申请日：2015-06-02

申请人： Tsung-Yi Huang ,  Kuo-Hsuan Lo ,  Wu-Te Weng

发明人： Tsung-Yi Huang ,  Kuo-Hsuan Lo ,  Wu-Te Weng

IPC分类号： H01L27/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/866

CPC分类号： H01L27/0255 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/66106 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/866

摘要： The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer.

摘要翻译： 本发明公开了一种瞬态电压抑制（TVS）装置及其制造方法。 TVS器件限制其两个端子之间的电压降不超过钳位电压。 TVS器件形成在堆叠衬底中，该衬底包括依次层叠的半导体衬底，P型第一外延层和第二外延层。 在TVS器件中，第一PN二极管串联连接到齐纳二极管，其中串联电路由第一浅沟槽隔离（STI）区域包围; 并且第二PN二极管与串联电路并联连接，其中第二PN二极管被第二STI区域包围。 第一STI区域和第​​二STI区域都从上表面延伸到第二外延层，而不是延伸到第一外延层。

公开(公告)号：US09105757B2

公开(公告)日：2015-08-11

申请号：US14040670

申请日：2013-09-28

申请人： Chih-Fang Huang ,  Tsung-Yi Huang ,  Chien-Wei Chiu ,  Tsung-Yu Yang ,  Ting-Fu Chang ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  Po-Chin Peng

发明人： Chih-Fang Huang ,  Tsung-Yi Huang ,  Chien-Wei Chiu ,  Tsung-Yu Yang ,  Ting-Fu Chang ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  Po-Chin Peng

IPC分类号： H01L29/872 ,  H01L29/66 ,  H01L29/868 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66212

摘要： The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

摘要翻译： 本发明公开了一种接合势垒肖特基（JBS）二极管及其制造方法。 JBS二极管包括：N型氮化镓（GaN）衬底; 形成在N型GaN衬底上的氮化镓铝（AlGaN）阻挡层; 在N型GaN衬底上形成的P型氮化镓（GaN）层; 至少部分地形成在AlGaN阻挡层上的阳极导电层，其中在所述阳极导电层的一部分和所述AlGaN阻挡层之间形成肖特基接触; 以及阴极导电层，其形成在N型GaN衬底上，其中在阴极导电层和N型GaN衬底之间形成欧姆接触，并且阴极导电层不直接连接到阳极导电层 。

公开(公告)号：US09105656B2

公开(公告)日：2015-08-11

申请号：US14055622

申请日：2013-10-16

申请人： Tsung-Yi Huang ,  Kuo-Hsuan Lo

发明人： Tsung-Yi Huang ,  Kuo-Hsuan Lo

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/337 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/66681 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/7835

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; agate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件包括：第一导电型衬底，其中形成隔离区以限定器件区域; 形成在第一导电类型衬底上的玛瑙; 在器件区域中分别形成并位于栅极两侧的源极和漏极，并掺杂有第二导电类型杂质; 第二导电型阱，其形成在第一导电类型基板中，并且从俯视图围绕漏极; 以及第一深沟槽隔离结构，其形成在第一导电类型基板中，并且从顶视图位于源极和漏极之间的第二导电类型阱中，其中第一深沟槽隔离结构的深度比 第二导电类型井从横截面图。

公开(公告)号：US20150091104A1

公开(公告)日：2015-04-02

申请号：US14041336

申请日：2013-09-30

申请人： Tsung-Yi Huang

发明人： Tsung-Yi Huang

IPC分类号： H01L29/06 ,  H01L29/78

CPC分类号： H01L29/0684 ,  H01L21/823892 ,  H01L29/0646 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/78 ,  H01L29/7816

摘要： The invention provides a semiconductor structure and a semiconductor device having such semiconductor structure. The semiconductor structure includes: a substrate; a first well having a first conductivity type, which is provided on the substrate; a second well having a second conductivity type and contacting the first well at a boundary in between in a lateral direction; and a plurality of mitigation regions having the first conductivity type or the second conductivity type, provided in the first well and being close to the boundary in a lateral direction and penetrating the first well in a vertical direction.

摘要翻译： 本发明提供一种具有这种半导体结构的半导体结构和半导体器件。 半导体结构包括：基板; 具有第一导电类型的第一阱，其设置在基板上; 第二阱具有第二导电类型，并且在横向方向上的边界处接触第一阱; 以及具有第一导电类型或第二导电类型的多个缓和区，设置在第一阱中并且在横向方向上接近边界并且在垂直方向上穿透第一阱。

公开(公告)号：US20140315358A1

公开(公告)日：2014-10-23

申请号：US13866766

申请日：2013-04-19

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L29/66

CPC分类号： H01L29/66893 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66901 ,  H01L29/808

摘要： The present invention discloses a manufacturing method of a junction field effect transistor (JFET). The manufacturing method includes: providing a substrate with a first conductive type, forming a channel region with a second conductive type, forming a field region with the first conductive type, forming a gate with the first conductive type, forming a source with the second conductive type, forming a drain with the second conductive type, and forming a lightly doped region with the second conductive type. The channel region is formed by an ion implantation process step, wherein the lightly doped region is formed by masking a predetermined region from accelerated ions of the ion implantation process step, and diffusing impurities with the second conductive type nearby the predetermined region into it with a thermal process step.

摘要翻译： 本发明公开了一种结型场效应晶体管（JFET）的制造方法。 该制造方法包括：提供具有第一导电类型的衬底，形成具有第二导电类型的沟道区，形成具有第一导电类型的场区，形成具有第一导电类型的栅极，形成具有第二导电 形成具有第二导电类型的漏极，以及形成具有第二导电类型的轻掺杂区域。 沟道区域通过离子注入工艺步骤形成，其中通过从离子注入工艺步骤的加速离子掩蔽预定区域并且将具有第二导电类型的杂质附近的预定区域的杂质扩散到其中以通过离子注入工艺步骤 热处理步骤。

公开(公告)号：US08729630B1

公开(公告)日：2014-05-20

申请号：US14146512

申请日：2014-01-02

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/66

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.