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    SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT
    1.
    发明申请
    SEMICONDUCTOR DEVICE HAVING NON-ORTHOGONAL ELEMENT 审中-公开
    具有非正交元素的半导体器件

    公开(公告)号：US20130320451A1

    公开(公告)日：2013-12-05

    申请号：US13486185

    申请日：2012-06-01

    申请人： Chia-Chu Liu ,  Shiao-Chian Yeh ,  Hong-Jang Wu ,  Kuei-Shun Chen

    发明人： Chia-Chu Liu ,  Shiao-Chian Yeh ,  Hong-Jang Wu ,  Kuei-Shun Chen

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L23/522 ,  H01L21/76895 ,  H01L27/0207 ,  H01L29/4238 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

    摘要翻译： 本公开提供了一种器件，包括第一栅极结构段和共线第二栅极结构段，以及第三栅极结构段和共线第四栅极结构段。 互连从第一栅极结构段延伸到第四栅极结构段。 互连设置在第一栅极结构段和第四栅极结构段之上。 互连可以形成在半导体器件的接触层上或与其共面。

    Method and apparatus for developing process
    4.
    发明授权
    Method and apparatus for developing process 有权
    开发过程的方法和装置

    公开(公告)号：US08703392B2

    公开(公告)日：2014-04-22

    申请号：US13602445

    申请日：2012-09-04

    申请人： Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

    发明人： Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

    IPC分类号： G03F7/26 ,  B05B7/00 ,  B05C11/00

    CPC分类号： G03F7/322

    摘要： The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical.

    摘要翻译： 本公开涉及制造半导体器件的方法。 该方法包括提供其上形成有材料层的基板; 在所述材料层上沉积光致抗蚀剂层，所述光致抗蚀剂层具有垂直尺寸; 将所述光致抗蚀剂层的区域暴露于辐射，所述暴露区域具有水平尺寸，其中所述垂直尺寸与所述水平尺寸的第一比例超过预定比率; 并且通过施加包含第一化学品和第二化学品的显影剂溶液，至少部分地显影所述光致抗蚀剂层以去除所述暴露区域，其中：所述第一化学品被配置为通过化学反应溶解所述光致抗蚀剂层的暴露区域; 第二化学品被配置为增强与光致抗蚀剂层接触的第一化学品的流动; 并且在第一化学品和第二化学品之间存在优化的第二比例。

    ENHANCED FINFET PROCESS OVERLAY MARK
    5.
    发明申请
    ENHANCED FINFET PROCESS OVERLAY MARK 有权
    加强FINFET工艺标准

    公开(公告)号：US20140065832A1

    公开(公告)日：2014-03-06

    申请号：US13602697

    申请日：2012-09-04

    申请人： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

    发明人： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

    IPC分类号： H01L21/308 ,  H01L23/544

    CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L27/0883 ,  H01L27/0886 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

    摘要翻译： 公开了适用于制造非平面电路器件的重叠标记和形成覆盖标记的方法。 示例性实施例包括接收具有有源器件区域和覆盖区域的衬底。 在基板上形成一个或多个电介质层和硬掩模。 图案化硬掩模以形成被配置为限定覆盖标记鳍的硬掩模层特征。 间隔物形成在图案化的硬掩模层上。 垫片进一步限定重叠标记鳍片和有源器件鳍片。 覆盖标记鳍被切割以形成用于定义覆盖度量的参考位置的鳍线端。 蚀刻电介质层和衬底以进一步限定覆盖标记鳍。

    Method and Apparatus for Developing Process
    7.
    发明申请
    Method and Apparatus for Developing Process 有权
    开发过程的方法和装置

    公开(公告)号：US20140065554A1

    公开(公告)日：2014-03-06

    申请号：US13602445

    申请日：2012-09-04

    申请人： Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

    发明人： Yu-Lun Liu ,  Chia-Chu Liu ,  Kuei-Shun Chen ,  Chung-Ming Wang ,  Ying-Hao Su

    IPC分类号： G03F7/20 ,  G03B27/32

    CPC分类号： G03F7/322

    摘要： The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a material layer formed thereon; depositing a photoresist layer on the material layer, the photoresist layer having a vertical dimension; exposing a region of the photoresist layer to radiation, the exposed region having a horizontal dimension, wherein a first ratio of the vertical dimension to the horizontal dimension exceeds a predetermined ratio; and developing the photoresist layer to remove the exposed region at least in part through applying a developer solution containing a first chemical and a second chemical, wherein: the first chemical is configured to dissolve the exposed region of the photoresist layer through a chemical reaction; the second chemical is configured to enhance flow of the first chemical that comes into contact with the photoresist layer; and an optimized second ratio exists between the first chemical and the second chemical.

    摘要翻译： 本公开涉及制造半导体器件的方法。 该方法包括提供其上形成有材料层的基板; 在所述材料层上沉积光致抗蚀剂层，所述光致抗蚀剂层具有垂直尺寸; 将所述光致抗蚀剂层的区域暴露于辐射，所述暴露区域具有水平尺寸，其中所述垂直尺寸与所述水平尺寸的第一比例超过预定比率; 并且通过施加包含第一化学品和第二化学品的显影剂溶液，至少部分地显影所述光致抗蚀剂层以去除所述暴露区域，其中：所述第一化学品被配置为通过化学反应溶解所述光致抗蚀剂层的暴露区域; 第二化学品被配置为增强与光致抗蚀剂层接触的第一化学品的流动; 并且在第一化学品和第二化学品之间存在优化的第二比例。

    Enhanced FinFET process overlay mark
    9.
    发明授权
    Enhanced FinFET process overlay mark 有权
    增强型FinFET工艺叠加标记

    公开(公告)号：US08822343B2

    公开(公告)日：2014-09-02

    申请号：US13602697

    申请日：2012-09-04

    申请人： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

    发明人： Chi-Wen Hsieh ,  Chi-Kang Chang ,  Chia-Chu Liu ,  Meng-Wei Chen ,  Kuei-Shun Chen

    IPC分类号： H01L21/308

    CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L27/0883 ,  H01L27/0886 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region. One or more dielectric layers and a hard mask are formed on the substrate. The hard mask is patterned to form a hard mask layer feature configured to define an overlay mark fin. Spacers are formed on the patterned hard mask layer. The spacers further define the overlay mark fin and an active device fin. The overlay mark fin is cut to form a fin line-end used to define a reference location for overlay metrology. The dielectric layers and the substrate are etched to further define the overlay mark fin.

    摘要翻译： 公开了适用于制造非平面电路器件的重叠标记和形成覆盖标记的方法。 示例性实施例包括接收具有有源器件区域和覆盖区域的衬底。 在基板上形成一个或多个电介质层和硬掩模。 图案化硬掩模以形成被配置为限定覆盖标记鳍的硬掩模层特征。 间隔物形成在图案化的硬掩模层上。 垫片进一步限定重叠标记鳍片和有源器件鳍片。 覆盖标记鳍被切割以形成用于定义覆盖度量的参考位置的鳍线端。 蚀刻电介质层和衬底以进一步限定覆盖标记鳍。