公开(公告)号：US06665212B1

公开(公告)日：2003-12-16

申请号：US10065032

申请日：2002-09-12

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1606

CPC分类号： G11C11/5621 ,  G11C16/30 ,  G11C2211/5634

摘要： The reference current generation circuit of a multiple bit flash memory. An identical boosted word-line voltage is applied to the gate terminal of reference memory cells in different reference current generation units and a different substrate voltage is applied to the substrate of each reference memory cell so that different reference currents are produced. This arrangement reduces different degree of shifting in the reference currents due to temperature and source voltage Vcc variation.

摘要翻译： 多位闪存的参考电流产生电路。 将相同的升压字线电压施加到不同参考电流产生单元中的参考存储器单元的栅极端子，并且将不同的衬底电压施加到每个参考存储器单元的衬底，使得产生不同的参考电流。 这种布置降低了由于温度和源电压Vcc变化引起的参考电流的不同移位程度。

公开(公告)号：US20050270844A1

公开(公告)日：2005-12-08

申请号：US11198684

申请日：2005-08-04

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C11/56 ,  G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

摘要： A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

公开(公告)号：US06785163B2

公开(公告)日：2004-08-31

申请号：US10387501

申请日：2003-03-14

申请人： Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： G11C1606

CPC分类号： G11C29/028 ,  G11C16/04 ,  G11C16/28 ,  G11C2029/5006

摘要： A trim circuit and method for tuning a current level of a reference cell in a flash memory that includes a sense amplifier to compare a cell current from a memory cell whose gate receives a word line signal voltage with a reference current from the reference cell whose gate receives a bias voltage produced by dividing the word line signal voltage by a voltage divider to thereby produce a sense signal. The voltage divider includes at least a programmable flash cell to serve as a variable resistor whose resistance is determined by programming the programmable flash cell by a programming/erasing circuit in reference to the programming of the memory cell.

摘要翻译： 一种微调电路和方法，用于调整闪速存储器中的参考单元的电流电平，该闪存存储器包括读出放大器，用于比较来自其栅极接收字线信号电压的存储单元的单元电流与参考电流的参考电流， 接收由分压器划分字线信号电压而产生的偏压，从而产生感测信号。 分压器至少包括可编程闪存单元，用作可变电阻器，其电阻通过编程/擦除电路参考存储器单元的编程对可编程闪存单元进行编程来确定。

公开(公告)号：US07173849B2

公开(公告)日：2007-02-06

申请号：US11198684

申请日：2005-08-04

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C16/02

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

摘要： A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

摘要翻译： 多级闪存的编程方法包括拍摄每次逐步向多级闪速存储器的门逐渐增加的编程电压，并且随后，拍摄向下减小的编程验证电压， 在最后一个程序验证电压被拍摄之后，在多级闪存中高电平并在多级闪存中拍摄附加的编程电压。 多级闪速存储器的擦除方法包括拍摄每次逐步向下逐渐减小到多级闪存的门的擦除电压，随后，拍摄向上增加的擦除验证电压以擦除多级闪存， 在最后擦除验证电压被拍摄之后，多级闪存中的电平和多级闪存中的附加电压。

公开(公告)号：US06917073B2

公开(公告)日：2005-07-12

申请号：US10643877

申请日：2003-08-20

申请人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115

摘要： To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

摘要翻译： 为了减少相邻存储单元之间的干扰，改进的ONO闪速存储器阵列在通道两侧的每个存储单元的通道的一侧或两个不同浓度的凹槽的一侧上注入一个口袋，从而导致不对称的存储单元 口袋 因此，当通过频带技术对ONO闪速存储器阵列进行编程或擦除时，相邻存储单元之间不会发生干扰，并且在读取过程中相邻存储单元之间的干扰也被抑制。

公开(公告)号：US20050040458A1

公开(公告)日：2005-02-24

申请号：US10643877

申请日：2003-08-20

申请人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Chih-Chieh Yeh ,  Tso-Hung Fan ,  Tao-Cheng Lu

IPC分类号： H01L27/115 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115

摘要： To reduce the disturbance between adjacent memory cells, an improved ONO flash memory array is implanted with a pocket on one side of the channel of each memory cell or two pockets of different concentrations on both sides of the channel, thereby resulting in memory cells with asymmetric pockets. Consequently, no disturbances occurred between adjacent memory cells when the ONO flash memory array is programmed or erased by band-to-band techniques, and the disturbances between adjacent memory cells are also suppressed during reading process.

摘要翻译： 为了减少相邻存储单元之间的干扰，改进的ONO闪速存储器阵列在通道两侧的每个存储单元的通道的一侧或两个不同浓度的凹槽的一侧上注入一个口袋，从而导致不对称的存储单元 口袋 因此，当通过频带技术对ONO闪速存储器阵列进行编程或擦除时，相邻存储单元之间不会发生干扰，并且在读取过程中相邻存储单元之间的干扰也被抑制。

公开(公告)号：US06687160B1

公开(公告)日：2004-02-03

申请号：US10064918

申请日：2002-08-29

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1606

CPC分类号： G11C16/12 ,  G11C5/147 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5634

摘要： A reference current generation circuit for the multiple bit flash memory provided by the present invention applies the same boosted word-line voltage to the gates of different reference current generation unit's reference cells, and uses different gate lengths from different reference cells to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.

摘要翻译： 本发明提供的用于多位闪速存储器的参考电流产生电路将相同的升压字线电压施加到不同参考电流产生单元的参考单元的栅极，并且使用来自不同参考单元的不同栅极长度来获得参考电流 需要不同的水平。 因此，它有效地解决了具有不同漂移的参考电流以及温度变化和电源电压Vcc的问题。

公开(公告)号：US06958934B2

公开(公告)日：2005-10-25

申请号：US10065761

申请日：2002-11-15

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C11/56 ,  G11C16/02

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5621

摘要： A programming method of the multi-level flash memory comprises shooting a programming voltage that is increasing upwards stepwise each time into the gate of the multi-level flash memory, and following, shooting a program verify voltage that is decreasing downwards to program a multi-level in the multi-level flash memory and shooting an additional programming voltage into the multi-level flash memory after the last program verify voltage is shot. An erasing method of the multi-level flash memory comprises shooting an erasing voltage that is decreasing downwards stepwise each time into a gate of the multi-level flash memory, and following, shooting a erase verify voltage that is increasing upwards to erase a multi-level in the multi-level flash memory and shooting an additional voltage into the multi-level flash memory after the last erase verify voltage is shot.

摘要翻译： 多级闪存的编程方法包括拍摄每次逐步向多级闪速存储器的门逐渐增加的编程电压，并且随后，拍摄向下减小的编程验证电压， 在最后一个程序验证电压被拍摄之后，在多级闪存中高电平并在多级闪存中拍摄附加的编程电压。 多级闪速存储器的擦除方法包括拍摄每次逐步向下逐渐减小到多级闪存的门的擦除电压，随后，拍摄向上增加的擦除验证电压以擦除多级闪存， 在最后擦除验证电压被拍摄之后，多级闪存中的电平和多级闪存中的附加电压。

公开(公告)号：US06643176B1

公开(公告)日：2003-11-04

申请号：US10064917

申请日：2002-08-29

申请人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Chih-Chieh Yeh ,  Tao-Cheng Lu

IPC分类号： G11C1606

CPC分类号： G11C16/30 ,  G11C8/08 ,  G11C11/5642 ,  G11C2211/5634

摘要： A reference current generation circuit for the multiple bit flash memory provided by the present invention applies the same boosted word-line voltage to a voltage dividing circuit of the different reference current generation unit, so as to generate a gate voltage for the different reference current generation unit's reference cell to obtain the reference currents with different levels that are needed. Therefore, it effectively solves the problem of the reference currents having different drifts along with the variance of the temperature and the power voltage Vcc.

摘要翻译： 由本发明提供的用于多位闪存的参考电流产生电路将相同的升压字线电压施加到不同参考电流产生单元的分压电路，以产生用于不同参考电流产生的栅极电压 单位的参考单元，以获得所需水平不同的参考电流。 因此，它有效地解决了具有不同漂移的参考电流以及温度变化和电源电压Vcc的问题。

公开(公告)号：US06790730B2

公开(公告)日：2004-09-14

申请号：US10156325

申请日：2002-05-24

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11253 ,  H01L21/26586 ,  H01L27/112

摘要： A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

摘要翻译： 描述了一种用于掩模只读存储器件的制造方法。 该方法提供衬底，并且在衬底上形成掺杂导电层。 之后，将掺杂的导电层图案化以形成多个棒状掺杂导电层，随后通过热氧化在基板上和棒状导电层上形成电介质层。 多个扩散区同时形成在基板中的棒状导电层的下方。 在电介质层上进一步形成图案化的导电层。