公开(公告)号：US07663410B2

公开(公告)日：2010-02-16

申请号：US11905796

申请日：2007-10-04

申请人： Chih-Haur Huang ,  Yuan-Kai Chu

发明人： Chih-Haur Huang ,  Yuan-Kai Chu

IPC分类号： H02M11/00

CPC分类号： H04L25/0278

摘要： A current-mode differential transmitter, receiving a single-end input voltage signal and accordingly generating a differential output current signal, is provided. The transmitter includes a first switch, a second switch and a current mirror. The first switch is coupled in a first current path and controlled by the single-end input voltage signal. The second switch is coupled in a second current path and controlled by an inverted signal of the single-end input voltage signal. The current mirror mirrors a reference current to the first current path when the first switch is turned on, and mirrors the reference current to the second current path when the second switch is turned on. The differential output current signal is derived from the currents on the first and second current paths.

摘要翻译： 提供了接收单端输入电压信号并因此产生差分输出电流信号的电流模式差分发射器。 发射机包括第一开关，第二开关和电流镜。 第一开关耦合在第一电流路径中并由单端输入电压信号控制。 第二开关耦合在第二电流路径中并由单端输入电压信号的反相信号控制。 当第一开关导通时，电流镜反射到第一电流路径的参考电流，并且当第二开关导通时将电流反射到第二电流路径的参考电流。 差分输出电流信号从第一和第二电流路径上的电流导出。

公开(公告)号：US20090091356A1

公开(公告)日：2009-04-09

申请号：US11905796

申请日：2007-10-04

申请人： Chih-Haur Huang ,  Yuan-Kai Chu

发明人： Chih-Haur Huang ,  Yuan-Kai Chu

IPC分类号： H02M11/00

CPC分类号： H04L25/0278

摘要： A current-mode differential transmitter, receiving a single-end input voltage signal and accordingly generating a differential output current signal, is provided. The transmitter includes a first switch, a second switch and a current mirror. The first switch is coupled in a first current path and controlled by the single-end input voltage signal. The second switch is coupled in a second current path and controlled by an inverted signal of the single-end input voltage signal. The current mirror mirrors a reference current to the first current path when the first switch is turned on, and mirrors the reference current to the second current path when the second switch is turned on. The differential output current signal is derived from the currents on the first and second current paths.

摘要翻译： 提供了接收单端输入电压信号并因此产生差分输出电流信号的电流模式差分发射器。 发射机包括第一开关，第二开关和电流镜。 第一开关耦合在第一电流路径中并由单端输入电压信号控制。 第二开关耦合在第二电流路径中并由单端输入电压信号的反相信号控制。 当第一开关导通时，电流镜反射到第一电流路径的参考电流，并且当第二开关导通时将电流反射到第二电流路径的参考电流。 差分输出电流信号从第一和第二电流路径上的电流导出。

公开(公告)号：US07177202B2

公开(公告)日：2007-02-13

申请号：US10711573

申请日：2004-09-25

申请人： Yuan-Kai Chu ,  Pen-Hsin Chen ,  Kuei-Hsiang Chen ,  Lin-Kai Bu

发明人： Yuan-Kai Chu ,  Pen-Hsin Chen ,  Kuei-Hsiang Chen ,  Lin-Kai Bu

IPC分类号： G11C7/00

CPC分类号： G11C7/1045

摘要： A method for accessing a single port memory is provided. A single port memory is used as a line buffer and divided into a plurality of memory blocks. The line buffer data is written into or read out from these memory blocks by turns with a special sequence corresponding to the operation mode; for example, a normal mode or a PLM mode. Therefore, the line buffer data can be written into or read out from the line buffer at the same time, and the size and cost of integrated circuit can be reduced.

摘要翻译： 提供了访问单个端口存储器的方法。 单个端口存储器被用作行缓冲器并被分成多个存储块。 行缓冲器数据以与操作模式对应的特殊顺序轮流写入或从这些存储器块读出; 例如，正常模式或PLM模式。 因此，行缓冲器数据可以同时被写入或从线缓冲器读出，并且可以减小集成电路的尺寸和成本。

公开(公告)号：US20060215063A1

公开(公告)日：2006-09-28

申请号：US11087497

申请日：2005-03-24

申请人： Jian-Jang Huang ,  Yuan-Kai Chu

发明人： Jian-Jang Huang ,  Yuan-Kai Chu

IPC分类号： H04N5/00

CPC分类号： H04B1/28 ,  H03D7/18 ,  H04N5/211 ,  H04N5/50

摘要： A circuit and a method for eliminating interference introduced from an image channel into a desired channel is described. The circuit includes a splitter and an adder. The splitter generates signals split from a received signal having frequency components within the desired and image channel. The adder adds together the signals output from the splitter. The circuit can be used in an TV tuner.

摘要翻译： 描述用于消除从图像信道引入到期望信道中的干扰的电路和方法。 该电路包括分路器和加法器。 分离器产生从具有期望和图像通道内的频率分量的接收信号分离的信号。 加法器将分离器输出的信号相加。 该电路可用于电视调谐器。

公开(公告)号：US07560969B2

公开(公告)日：2009-07-14

申请号：US11898157

申请日：2007-09-10

申请人： Yuan-Kai Chu

发明人： Yuan-Kai Chu

IPC分类号： H03L5/00 ,  H03K5/08

CPC分类号： H03F3/45968 ,  H03F3/45475 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03F2203/45212 ,  H03F2203/45521 ,  H03F2203/45544 ,  H03F2203/45588 ,  H04L25/0272 ,  H04L25/0292

摘要： A receiver of a high speed digital interface includes at least one differential amplifier, a pair of resistive elements, a current source and a pair of transistors. The differential amplifier receives a small differential signal at a pair of input terminals and outputs an amplified differential signal. Each of the resistive elements has one end coupled to one of the input terminals of the differential amplifier and the other end receiving a reference voltage. The pair of transistors has drains respectively coupled to the input terminals of the differential amplifier, sources commonly coupled to the current source and gates receiving a differential feedback signal derived from the amplified differential signal.

摘要翻译： 高速数字接口的接收器包括至少一个差分放大器，一对电阻元件，电流源和一对晶体管。 差分放大器在一对输入端接收小的差分信号，并输出放大的差分信号。 每个电阻元件的一端耦合到差分放大器的一个输入端子，另一端接收参考电压。 该对晶体管具有分别耦合到差分放大器的输入端的漏极，源极通常耦合到电流源，栅极接收从放大的差分信号导出的差分反馈信号。

公开(公告)号：US07495514B2

公开(公告)日：2009-02-24

申请号：US11356293

申请日：2006-02-17

申请人： Da-Rong Huang ,  Huey-Ru Chuang ,  Yuan-Kai Chu

发明人： Da-Rong Huang ,  Huey-Ru Chuang ,  Yuan-Kai Chu

IPC分类号： H03G3/12

CPC分类号： H03F1/26 ,  H03F3/195 ,  H03F3/347 ,  H03F3/4508 ,  H03F2200/294 ,  H03F2200/36 ,  H03F2200/372 ,  H03G1/007

摘要： A low noise amplifier including a first-stage signal amplifier, a second-stage signal amplifier and a gain control unit is disclosed. The first-stage signal amplifier is for receiving an input signal and outputting a first output signal accordingly. The second-stage signal amplifier is coupled to the first-stage signal amplifier for outputting a second output signal according to the first output signal. The second-stage signal amplifier includes a first output transistor for outputting the second output signal. The gain control unit includes a first variable resistance device coupled to an input terminal of the first output transistor for adjusting voltage gain of the second output signal.

摘要翻译： 公开了一种包括第一级信号放大器，第二级信号放大器和增益控制单元的低噪声放大器。 第一级信号放大器用于接收输入信号并相应地输出第一输出信号。 第二级信号放大器耦合到第一级信号放大器，用于根据第一输出信号输出第二输出信号。 第二级信号放大器包括用于输出第二输出信号的第一输出晶体管。 增益控制单元包括耦合到第一输出晶体管的输入端的第一可变电阻器件，用于调节第二输出信号的电压增益。

公开(公告)号：US20110095737A1

公开(公告)日：2011-04-28

申请号：US12606468

申请日：2009-10-27

申请人： Yuan-Kai Chu ,  Hui-Min Wang

发明人： Yuan-Kai Chu ,  Hui-Min Wang

IPC分类号： G05F1/10

CPC分类号： G05F1/575

摘要： A voltage regulator and an integrated circuit using the voltage regulator is provided. The voltage regulator has a bandgap reference circuit, an operational amplifier, a power transistor and a voltage divider. The bandgap reference circuit generates a bandgap reference voltage. The operational amplifier receives the bandgap reference voltage and a feedback voltage to output a control signal for the power transistor. The power transistor is powered by a first voltage source and transforms the first voltage source to a second voltage source according to the control signal. The second voltage source is divided by the voltage divider to generate the feedback voltage and is further used in powering the bandgap reference circuit and the operational amplifier.

摘要翻译： 提供了使用电压调节器的电压调节器和集成电路。 电压调节器具有带隙参考电路，运算放大器，功率晶体管和分压器。 带隙参考电路产生带隙参考电压。 运算放大器接收带隙参考电压和反馈电压以输出功率晶体管的控制信号。 功率晶体管由第一电压源供电，并根据控制信号将第一电压源转换为第二电压源。 第二电压源由分压器分压以产生反馈电压，并进一步用于为带隙基准电路和运算放大器供电。

公开(公告)号：US07206007B2

公开(公告)日：2007-04-17

申请号：US10906139

申请日：2005-02-04

申请人： Chung-Hsun Huang ,  Yuan-Kai Chu ,  Kuei-Hsiang Chen

发明人： Chung-Hsun Huang ,  Yuan-Kai Chu ,  Kuei-Hsiang Chen

IPC分类号： G06T15/00

CPC分类号： G06F3/14 ,  G09G5/18

摘要： A method for video processing which provides a scaled image using two different clock frequencies is provided. The method receives source pixel data using a first clock signal and scales the source pixel data to destination pixel data. After that, the destination pixel data is provided using a second clock signal having a second clock frequency and a third clock signal having a third clock frequency during blanking period and active period, respectively.

摘要翻译： 提供了一种使用两个不同时钟频率提供缩放图像的视频处理方法。 该方法使用第一时钟信号接收源像素数据，并将源像素数据缩放到目标像素数据。 之后，分别使用具有第二时钟频率的第二时钟信号和在消隐周期和有效周期期间具有第三时钟频率的第三时钟信号来提供目的地像素数据。

公开(公告)号：US20060176320A1

公开(公告)日：2006-08-10

申请号：US10906139

申请日：2005-02-04

申请人： Chung-Hsun Huang ,  Yuan-Kai Chu ,  Kuei-Hsiang Chen

发明人： Chung-Hsun Huang ,  Yuan-Kai Chu ,  Kuei-Hsiang Chen

IPC分类号： G09G5/00

CPC分类号： G06F3/14 ,  G09G5/18

摘要： A method for video processing which provides a scaled image using two different clock frequencies is provided. The method receives source pixel data using a first clock signal and scales the source pixel data to destination pixel data. After that, the destination pixel data is provided using a second clock signal having a second clock frequency and a third clock signal having a third clock frequency during blanking period and active period, respectively.

摘要翻译： 提供了一种使用两个不同时钟频率提供缩放图像的视频处理方法。 该方法使用第一时钟信号接收源像素数据，并将源像素数据缩放到目标像素数据。 之后，分别使用具有第二时钟频率的第二时钟信号和在消隐周期和有效周期期间具有第三时钟频率的第三时钟信号来提供目的地像素数据。

公开(公告)号：US08493260B2

公开(公告)日：2013-07-23

申请号：US13240806

申请日：2011-09-22

申请人： Yuan-Kai Chu ,  Jin-Fu Lin

发明人： Yuan-Kai Chu ,  Jin-Fu Lin

IPC分类号： H03M1/14

CPC分类号： H03M1/14

摘要： A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.

摘要翻译： 用于在转换阶段将模拟输入转换成N位数字输出的SAR ADC包括：三个比较器，每两个电容器子阵列分别耦合到三个比较器，其中使用两个电容器子阵列 用于对模拟输入进行采样并为相应的比较器提供两个输入; 以及耦合到三个比较器和三个电容器阵列的SAR逻辑，用于在每个转换子相中，将每个电容器子阵列的两个选定的电容器耦合到一组确定的参考电平，耦合两个选择的电容器 在前一转换子阶段中，将每个电容器子阵列转换成基于在前一转换子相中从三个比较器输出的一组数据而获得的一组调整参考电平，然后产生N位的两位， 通过对从三个比较器输出的一组数据进行编码来进行位数字输出。