公开(公告)号：US06635565B2

公开(公告)日：2003-10-21

申请号：US09789357

申请日：2001-02-20

申请人： Chih-Ning Wu ,  Chan-Lon Yang ,  Sun-Chieh Chien

发明人： Chih-Ning Wu ,  Chan-Lon Yang ,  Sun-Chieh Chien

IPC分类号： H01L214763

CPC分类号： H01L21/02074 ,  C23F1/30 ,  H01L21/02063 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/76814

摘要： A method of cleaning a dual damascene structure includes forming a first conductive layer in a substrate. A dielectric layer is formed over the substrate. A dual damascene opening is formed in the dielectric layer to expose the first conductive layer. A H2O2 based aqueous solution is used to remove polymer residues in the dual damascene opening. A temperature of the H2O2 based aqueous solution is controlled so that the first conductive layer is not corroded. A diluted HF solution or a diluted HF and HCl solution is used to remove the polymer residues. A second conductive layer is formed over the substrate to fill the dual damascene opening. A chemical mechanical polishing process is performed with the dielectric layer serving as a polishing stop to remove the second conductive layer outside the dual damascene opening. A H2O2 based aqueous solution is used to clean the hydrocarbon particulates from the chemical mechanically polishing step. A diluted HF solution or a diluted HF and HCl solution is used to remove the slurry residues, such as silicon oxide of the slurry, from the chemical mechanical polishing step.

公开(公告)号：US06733597B2

公开(公告)日：2004-05-11

申请号：US09841817

申请日：2001-04-24

申请人： Chih-Ning Wu ,  Sun-Chieh Chien

发明人： Chih-Ning Wu ,  Sun-Chieh Chien

IPC分类号： B08B300

CPC分类号： H01L21/76814 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76838 ,  Y10S134/902 ,  Y10S438/906

摘要： A method is provided for cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer exposing the first metal layer. Next, a post-etching cleaning step is carried out to clean the dual damascene opening using a fluorine-based solvent. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.

摘要翻译： 提供了一种清洗双镶嵌结构的方法。 依次在基板上形成第一金属层，盖层和电介质层。 然后在电介质层中形成双镶嵌开口，并且覆盖层露出第一金属层。 接下来，进行后蚀刻清洗工序，使用氟系溶剂清洗双镶嵌开口。 然后，在第二金属层填充到双镶嵌开口之前，溅射氩气等离子体以清洁双镶嵌开口。

公开(公告)号：US06692580B2

公开(公告)日：2004-02-17

申请号：US10407626

申请日：2003-04-04

申请人： Chih-Ning Wu ,  Sun-Chieh Chien

发明人： Chih-Ning Wu ,  Sun-Chieh Chien

IPC分类号： B08B300

CPC分类号： H01L21/76814 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76807 ,  H01L21/76838 ,  Y10S134/902 ,  Y10S438/906

摘要： A method of cleaning a dual damascene structure. A first metal layer, a cap layer, and a dielectric layer are formed on a substrate in sequence. Then a dual damascene opening is formed in the dielectric layer and the cap layer, exposing the first metal layer. Then, a post-etching cleaning step is carried out to clean the dual damascene opening, and there are two types of cleaning methods. The first method uses a fluorine-based solvent to clean the dual damascene opening. An alternative cleaning method uses a hydrogen peroxide based solvent at a high temperature, followed by a hydrofluoric acid solvent cleaning step. Then, an argon gas plasma is sputtered to clean the dual damascene opening before a second metal layer fills in the dual damascene opening.

摘要翻译： 一种清洗双镶嵌结构的方法。 依次在基板上形成第一金属层，盖层和电介质层。 然后在电介质层和盖层中形成双镶嵌开口，露出第一金属层。 然后，执行后蚀刻清洁步骤以清洁双镶嵌开口，并且存在两种类型的清洁方法。 第一种方法使用氟类溶剂清洗双镶嵌开口。 另一种清洗方法是在高温下使用基于过氧化氢的溶剂，然后使用氢氟酸溶剂清洗步骤。 然后，在第二金属层填充到双镶嵌开口之前，溅射氩气等离子体以清洁双镶嵌开口。

公开(公告)号：US20070072378A1

公开(公告)日：2007-03-29

申请号：US11463299

申请日：2006-08-08

申请人： Chih-Ning Wu ,  Chung - Ju Lee ,  Wei-Tsun Shiau

发明人： Chih-Ning Wu ,  Chung - Ju Lee ,  Wei-Tsun Shiau

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed. In the method, a silicon nitride spacer is formed and will be removed after an ion implantation process used to form a source/drain region and a salicide process used to form a metal silicide layer on the surface of the source/drain region and the gate electrode. The metal silicide layer is formed to comprise silicon (Si), nickel (Ni) and at least one metal selected from a group consisting of iridium (Ir), iron (Fe), cobalt (Co), platinum (Pt), palladium (Pd), molybdenum (Mo), and tantalum (Ta); therefore, when the silicon nitride spacer is removed by etching, the metal silicide layer is not damaged.

摘要翻译： 公开了一种制造金属氧化物半导体晶体管器件的方法。 在该方法中，形成氮化硅间隔物，并且在用于形成源极/漏极区域的离子注入工艺和用于在源极/漏极区域和栅极的表面上形成金属硅化物层的自对准硅化物工艺之后将被去除 电极。 金属硅化物层形成为包括硅（Si），镍（Ni）和选自铱（Ir），铁（Fe），钴（Co），铂（Pt），钯（ Pd），钼（Mo）和钽（Ta）; 因此，当通过蚀刻除去氮化硅间隔物时，金属硅化物层不被损坏。

公开(公告)号：US20070054447A1

公开(公告)日：2007-03-08

申请号：US11221487

申请日：2005-09-07

申请人： Hsin Tai ,  Chung-Ju Lee ,  Chih-Ning Wu

发明人： Hsin Tai ,  Chung-Ju Lee ,  Chih-Ning Wu

IPC分类号： H01L21/8234 ,  H01L21/302 ,  H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： A multi-step etching method is provided. First, a substrate including a gate over the substrate and a spacer over the gate is provided. Then, an anisotropic etching step is performed for etching a first region and a second region in the substrate at two sides of the gate. Thereafter, an isotropic etching step is performed for etching a first external region under the spacer and adjacent to the first region, and etching a second external region under the spacer and adjacent to the second region. Then, a filling step is performed for filling a material into the first region, the first external region, the second region and the second external region.

摘要翻译： 提供了多步蚀刻方法。 首先，提供包括在衬底上的栅极和栅极上的间隔物的衬底。 然后，进行各向异性蚀刻步骤，以蚀刻栅极两侧的基板中的第一区域和第二区域。 此后，进行各向同性蚀刻步骤，用于蚀刻间隔物下方的第一外部区域并与第一区域相邻，并且蚀刻间隔物下方的第二外部区域并与第二区域相邻。 然后，进行用于将材料填充到第一区域，第一外部区域，第二区域和第二外部区域中的填充步骤。

公开(公告)号：US20050239285A1

公开(公告)日：2005-10-27

申请号：US10709278

申请日：2004-04-26

申请人： Wen-Liang Lien ,  Charlie CJ Lee ,  Chih-Ning Wu ,  Jain-Hon Chen

发明人： Wen-Liang Lien ,  Charlie CJ Lee ,  Chih-Ning Wu ,  Jain-Hon Chen

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76811 ,  H01L21/76813

摘要： A method for avoiding resist poisoning during a damascene process is disclosed. A semiconductor substrate is provided with a low-k dielectric layer (k≦2.9) thereon, a SiC layer over the low-k dielectric layer, and a blocking layer over the SiC layer. The blocking layer is used to prevent unpolymerized precursors diffused out from the low-k dielectric layer from contacting an overlying resist. A bottom anti-reflection coating (BARC) layer is formed on the blocking layer. A resist layer is formed on the BARC layer, the resist layer having an opening to expose a portion of the BARC layer. A damascene structure is formed in the low-k dielectric layer by etching the BARC layer, the blocking layer, the SiC layer, and the low-k dielectric layer through the opening.

摘要翻译： 公开了一种在大马士革过程中避免抗蚀剂中毒的方法。 在半导体衬底上设置有低k电介质层（k <= 2.9），在低k电介质层上的SiC层和在SiC层上的阻挡层。 阻挡层用于防止从低k电介质层扩散的未聚合的前体与上覆抗蚀剂接触。 在阻挡层上形成底部防反射涂层（BARC）层。 在BARC层上形成抗蚀剂层，抗蚀剂层具有露出BARC层的一部分的开口。 通过开口蚀刻BARC层，阻挡层，SiC层和低k电介质层，在低k电介质层中形成镶嵌结构。

公开(公告)号：US06794292B2

公开(公告)日：2004-09-21

申请号：US09682054

申请日：2001-07-16

申请人： Chih-Ning Wu

发明人： Chih-Ning Wu

IPC分类号： H01L21302

CPC分类号： H01L21/02063 ,  C23G1/00 ,  H01L21/32134 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838

摘要： An extrusion-free wet cleaning process for post-etch Cu-dual damascene structures is developed. The process includes the following steps: (1). providing a wafer having a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an N+ diffusion region of the silicon substrate, and a trench structure formed on the via structure; (2). applying a diluted H2O2 solution on the wafer to slightly oxidize the surface of the exposed Cu wiring line; (3). washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NH4F or NH2OH; and (4). providing means for preventing Cu reduction reactions on the Cu wiring line.

摘要翻译： 开发了一种用于后蚀刻铜双镶嵌结构的无挤出湿法清洗工艺。 该过程包括以下步骤：（1）。 提供具有硅衬底和至少一个后蚀刻Cu-双镶嵌结构的晶片，所述后蚀刻Cu-双镶嵌结构具有通孔结构，其暴露与N +扩散电连接的Cu布线的一部分 硅衬底的区域和形成在通孔结构上的沟槽结构; （2）。 将稀释的H 2 O 2溶液施加在晶片上以稍微氧化暴露的Cu布线的表面; （3）。 通过含有稀释的HF，NH4F或NH2OH的酸性氧化铜清洗溶液洗涤在氧化步骤中产生的氧化铜; 和（4）。 提供了防止Cu布线上的Cu还原反应的手段。

公开(公告)号：US07338910B2

公开(公告)日：2008-03-04

申请号：US11162952

申请日：2005-09-29

申请人： Chung-Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

发明人： Chung-Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76834 ,  H01L21/28518 ,  H01L21/31111

摘要： A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on the top or the surface of the semiconductor substrate and the electrode; and removing the spacer by steps of performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant. With respect to another aspect, a method of removing a spacer is also disclosed. The method includes performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant.

摘要翻译： 公开了制造半导体器件的方法。 该方法包括在半导体衬底上限定电极; 在所述电极的至少一个侧壁上形成间隔物; 在所述半导体衬底上使用所述间隔件作为掩模进行处理操作，并在所述半导体衬底和所述电极的顶部或表面上形成材料层; 并且通过在100℃至150℃的温度范围内进行湿蚀刻工艺的步骤去除间隔物，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。 关于另一方面，还公开了一种去除间隔物的方法。 该方法包括在100℃至150℃范围内的温度下进行湿蚀刻工艺，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。

公开(公告)号：US20070075379A1

公开(公告)日：2007-04-05

申请号：US11380212

申请日：2006-04-26

申请人： Chih-Ning Wu ,  Chung - Ju Lee ,  Wei-Tsun Shiau

发明人： Chih-Ning Wu ,  Chung - Ju Lee ,  Wei-Tsun Shiau

IPC分类号： H01L21/20 ,  H01L29/76

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

摘要： A metal-oxide-semiconductor transistor device is disclosed, in which, a silicon nitride spacer has been formed but is removed after an ion implantation process to form a source/drain region and a salicide process to form a metal silicide layer on the surface of the source/drain region and the gate electrode are performed. The metal silicide layer comprises silicon, nickel and at least one metal selected from a group consisting of iridium, iron, cobalt, platinum, palladium, molybdenum, and tantalum; therefore, when the silicon nitride spacer is removed by etching, the metal silicide layer is not damaged.

摘要翻译： 公开了一种金属氧化物半导体晶体管器件，其中已经形成了氮化硅间隔物，但是在离子注入工艺之后被去除以形成源极/漏极区域和自对准硅化物工艺以在其表面上形成金属硅化物层 源极/漏极区域和栅极电极。 金属硅化物层包括硅，镍和选自铱，铁，钴，铂，钯，钼和钽中的至少一种金属; 因此，当通过蚀刻除去氮化硅间隔物时，金属硅化物层不被损坏。

公开(公告)号：US20070072402A1

公开(公告)日：2007-03-29

申请号：US11162952

申请日：2005-09-29

申请人： Chung - Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

发明人： Chung - Ju Lee ,  Chih-Ning Wu ,  Wei-Tsun Shiau

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/28518 ,  H01L21/31111

摘要： A method of fabricating a semiconductor device is disclosed. The method includes defining an electrode on a semiconductor substrate; forming a spacer on at least one sidewall of the electrode; performing a process operation on the semiconductor substrate using the spacer as a mask and forming a material layer on the top or the surface of the semiconductor substrate and the electrode; and removing the spacer by steps of performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant. With respect to another aspect, a method of removing a spacer is also disclosed. The method includes performing a wet etching process at a temperature in a range of 100° C. to 150° C. to etch the spacer using an acid solution containing phosphoric acid as an etchant.

摘要翻译： 公开了制造半导体器件的方法。 该方法包括在半导体衬底上限定电极; 在所述电极的至少一个侧壁上形成间隔物; 在所述半导体衬底上使用所述间隔件作为掩模进行处理操作，并在所述半导体衬底和所述电极的顶部或表面上形成材料层; 并且通过在100℃至150℃的温度范围内进行湿蚀刻工艺的步骤去除间隔物，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。 关于另一方面，还公开了一种去除间隔物的方法。 该方法包括在100℃至150℃范围内的温度下进行湿蚀刻工艺，以使用含有磷酸作为蚀刻剂的酸溶液蚀刻间隔物。