公开(公告)号：US06872629B2

公开(公告)日：2005-03-29

申请号：US10722647

申请日：2003-11-26

申请人： Chih-Yuan Hsiao ,  Yi-Nan Chen

发明人： Chih-Yuan Hsiao ,  Yi-Nan Chen

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/10864

摘要： A method of forming a memory cell with a single sided buried strap. A collar oxide layer is formed on the sidewall of a trench. A conductive layer fills the trench. The conductive layer and the collar oxide layer are partially removed to form an opening having first and second sidewalls. The remaining collar oxide layer is lower than the remaining conductive layer. An angle implantation with F ions is performed on the first sidewall. A thermal oxidation process is performed to form a first oxide layer on the first sidewall and a second oxide layer on the second sidewall. The first oxide layer is thicker than the second oxide layer. The second oxide layer is removed to expose the second sidewall. A buried strap is formed at the bottom of the opening, insulated from the first sidewall by the first oxide layer.

摘要翻译： 一种用单面埋置带形成存储单元的方法。 环状氧化物层形成在沟槽的侧壁上。 导电层填充沟槽。 导电层和套环氧化物层被部分去除以形成具有第一和第二侧壁的开口。 剩余的环状氧化物层比剩余的导电层低。 在第一侧壁上进行具有F离子的角度注入。 进行热氧化处理以在第一侧壁上形成第一氧化物层，在第二侧壁上形成第二氧化物层。 第一氧化物层比第二氧化物层厚。 去除第二氧化物层以暴露第二侧壁。 在开口的底部形成掩埋带，通过第一氧化物层与第一侧壁绝缘。

公开(公告)号：US07211483B2

公开(公告)日：2007-05-01

申请号：US11068173

申请日：2005-02-28

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。

公开(公告)号：US20050001256A1

公开(公告)日：2005-01-06

申请号：US10691173

申请日：2003-10-22

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

公开(公告)号：US06790735B2

公开(公告)日：2004-09-14

申请号：US10449297

申请日：2003-05-29

申请人： Hui-Min Mao ,  Sheng-Tsung Chen ,  Yi-Nan Chen ,  Bo-Ching Jiang ,  Chih-Yuan Hsiao

发明人： Hui-Min Mao ,  Sheng-Tsung Chen ,  Yi-Nan Chen ,  Bo-Ching Jiang ,  Chih-Yuan Hsiao

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L27/105 ,  H01L27/11 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming source/drain regions in semiconductor devices. First, a substrate having at least one gate structure is provided. Next, first, second, and third insulating spacers are successively formed over the sidewall of the gate structure. Subsequently, ion implantation is performed on the substrate on both sides of the gate structure using the third insulating spacer as a mask to form first doping regions. After the third insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the second insulating spacer as a mask to form second doping regions serving as source/drain regions with the first doping regions. Finally, after the second insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the first insulating spacer as a mask to form third doping regions, thereby preventing punchthrough.

公开(公告)号：US07009236B2

公开(公告)日：2006-03-07

申请号：US10691173

申请日：2003-10-22

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L27/108

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。

公开(公告)号：US20050167719A1

公开(公告)日：2005-08-04

申请号：US11068173

申请日：2005-02-28

申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/10864 ,  H01L27/10867

摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。

公开(公告)号：US20050048654A1

公开(公告)日：2005-03-03

申请号：US10792345

申请日：2004-03-03

申请人： Wen-Bin Wu ,  Chih-Yuan Hsiao ,  Hui-Min Mao

发明人： Wen-Bin Wu ,  Chih-Yuan Hsiao ,  Hui-Min Mao

IPC分类号： G03F7/20 ,  G03F9/00 ,  G01N31/00

CPC分类号： G03F9/7019 ,  G03F7/70633 ,  G03F9/7011

摘要： A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.

公开(公告)号：US11253867B2

公开(公告)日：2022-02-22

申请号：US16655564

申请日：2019-10-17

申请人： Chih-Yuan Hsiao ,  Yu-Chih Hsiao

发明人： Chih-Yuan Hsiao ,  Yu-Chih Hsiao

IPC分类号： B02C19/00 ,  B02C13/286 ,  B02C13/288

摘要： Dry nano-sizing equipment with fluid mobility effect dryly processes viewable fine-grained substances into a nano-sized dimension by high-pressure airflow resulted from a pressure-generating unit, as well as high-speed fluid and high mechanical momentum generated in a pressure cylinder by high-speed rotation of a booster impeller.

公开(公告)号：US06987053B2

公开(公告)日：2006-01-17

申请号：US10792345

申请日：2004-03-03

申请人： Wen-Bin Wu ,  Chih-Yuan Hsiao ,  Hui-Min Mao

发明人： Wen-Bin Wu ,  Chih-Yuan Hsiao ,  Hui-Min Mao

IPC分类号： H01L21/76

CPC分类号： G03F9/7019 ,  G03F7/70633 ,  G03F9/7011

摘要： A method for evaluating reticle registration between two reticle patterns. A wafer is defined and etched to form a first exposure pattern, by photolithography with a first reticle having a first reticle pattern thereon. A photoresist layer is formed over the wafer and defined as a second exposure pattern, by photolithography with a second reticle having a second reticle pattern thereon. A deviation value between the first and second exposure patterns is measured by a CD-SEM. The deviation value is calibrated according to the scaling degree and the overlay offset to obtain a registration data. The reticle registration between the two reticle patterns is evaluated based on the registration data.

摘要翻译： 一种用于评估两个掩模版图案之间的掩模版配准的方法。 通过用其上具有第一掩模版图案的第一掩模版通过光刻来限定和蚀刻晶片以形成第一曝光图案。 在晶片上形成光致抗蚀剂层，并通过光刻法将其定义为第二曝光图案，其上具有第二掩模版图案的第二掩模版。 通过CD-SEM测量第一和第二曝光图案之间的偏差值。 根据缩放程度和覆盖偏移校正偏差值，以获得注册数据。 基于登记数据评价两个掩模图案之间的掩模版登记。

公开(公告)号：US06699756B1

公开(公告)日：2004-03-02

申请号：US09715658

申请日：2000-11-17

申请人： Chih-Yuan Hsiao

发明人： Chih-Yuan Hsiao

IPC分类号： H01L21336

CPC分类号： H01L27/11

摘要： A method for forming four transistors static-random-access-memory. The method comprises the steps of: providing a substrate which at least comprises a cell region and periphery region, wherein the cell region comprises a first P-type region, a second P-type region, a first N-type region and a second N-type region, the periphery region comprises numerous periphery P-type regions and numerous periphery N-type regions; covering the first P-type region, the second P-type region and the periphery P-type region by a first photoresist; forming numerous N-type sources and numerous N-type drains in the first P-type region, the second P-type region and the periphery P-type regions; removing the first photoresists using a second photoresist to cover the periphery N-type regions and some the N-type drains which are located in both the first N-type region and the second N-type regions and performing a large angle implanting process to form numerous P-type enlarged drains and numerous P-type enlarged sources in the periphery P-type regions, the first P-type region and the P-type second region, wherein numerous P-type extra sources also are formed on outside of some the N-type drains which are located in both the first N-type region and the second N-type region.

摘要翻译： 一种形成四个晶体管静态随机存取存储器的方法。 该方法包括以下步骤：提供至少包括单元区域和外围区域的基板，其中单元区域包括第一P型区域，第二P型区域，第一N型区域和第二N型区域 周边区域包括多个周边P型区域和许多周边N型区域; 通过第一光致抗蚀剂覆盖第一P型区域，第二P型区域和周边P型区域; 在第一P型区域，第二P型区域和周边P型区域中形成多个N型源极和许多N型漏极; 使用第二光致抗蚀剂去除第一光致抗蚀剂以覆盖位于第一N型区域和第二N型区域中的周边N型区域和一些N型漏极，并执行大角度注入工艺以形成 在外围P型区域，第一P型区域和P型第二区域中的多个P型放大漏斗和多个P型放大源，其中许多P型额外源还形成在一些 N型排水管位于第一N型区域和第二N型区域中。