公开(公告)号：US06498759B2

公开(公告)日：2002-12-24

申请号：US09752119

申请日：2000-12-29

Applicant: Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho

Inventor： Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho

IPC: G11C700

CPC classification number: G06F1/26 ,  G11C5/04 ,  G11C5/06 ,  G11C5/14 ,  G11C5/143 ,  G11C8/06 ,  H05K1/0246 ,  H05K1/0262 ,  H05K1/14 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10022 ,  H05K2201/10159

Abstract: A system can produce a suitable voltage for powering the memory modules plugged into the memory module slots of a motherboard. A power-good signal is issued when the motherboard is powered up. A power safety device on the motherboard then issues a 2.5V to the memory module slot. If DDR DRAM type of memory modules are not detected after a while, the power safety device will turn off the 2,5V supply and provide a 3.3V, which is suitable for SDRAM type memory modules.This invention avoids sending a 3.3V to DDR DRAM modules, thereby burning the memory chip. The presence of DDR DRAM modules can be detected by a general-purpose purpose input/output port through accessing the recorded data in the EEPROM of the memory module. Alternatively, memory module type can be determined by sending out a low-current pulse signal to the memory module slot. Hence, a suitable voltage source is automatically provided to power the memory modules in the slots.

Abstract translation: 系统可以产生合适的电压，用于为插入主板的存储器模块槽中的存储器模块供电。 主板上电时发出电源良好信号。 主板上的电源安全设备然后向内存模块插槽发出2.5V电压。 如果DDR DRAM类型的存储器模块一段时间没有被检测到，电源安全设备将关闭2,5V电源并提供3.3V，这适用于SDRAM型存储器模块。本发明避免了将3.3V发送到DDR DRAM模块，从而烧录存储芯片。 通过访问存储器模块的EEPROM中的记录数据，可以通过通用目的输入/输出端口来检测DDR DRAM模块的存在。 或者，可以通过向存储器模块插槽发送低电流脉冲信号来确定存储器模块类型。 因此，自动提供合适的电压源来为插槽中的存储器模块供电。

公开(公告)号：US06563338B2

公开(公告)日：2003-05-13

申请号：US09921950

申请日：2001-08-03

Applicant: Ching-Fu Chuang ,  Nai-Shung Chang

Inventor： Ching-Fu Chuang ,  Nai-Shung Chang

IPC: H03K1716

CPC classification number: H03K19/01721 ,  H03K19/0016

Abstract: A control circuit, a chipset and a method capable of saving the terminal resistors on a motherboard. Through the determination of connection of a pull-up enable line to a first voltage source Vdd via a resistor, an equivalent resistance is set between the source terminal and the drain terminal of a field effect transistor. The equivalent resistance is almost identical to the terminal resistor and hence can replace the resistor on the motherboard. When the pull-up enable line is connected to the first voltage source Vdd via a resistor, an equivalent resistance of about 45-60&OHgr; is established between the source and drain terminal of the field effect transistor. The equivalent resistance is connected in parallel with an input/output pad and a second voltage source Vtt to replace the original externally connected terminal resistor rt2 at the other end of the bus. If the pull-up enable line is not connected to a first voltage source Vdd via a resistor, the field effect transistor is cut off and an infinite equivalent resistance is created between the source and the drain terminal. The infinite resistance is connected in parallel between the input/output pad and the second voltage source Vtt. The infinite equivalent resistance has little effect on any externally connected terminal resistor rt2 at the other end of the bus. Hence, through enabling or disabling the pull-up enable line, manufacturers are free to choose whether to save output power to the terminal resistor rt2 at the other end of the bus or not.

Abstract translation: 一种控制电路，芯片组和能够在主板上保存终端电阻的方法。 通过经由电阻器确定上拉使能线与第一电压源Vdd的连接，在场效应晶体管的源极端子和漏极端子之间设置等效电阻。 等效电阻几乎与端子电阻相同，因此可以替代主板上的电阻。 当上拉使能线通过电阻连接到第一电压源Vdd时，在场效应晶体管的源极和漏极端之间建立约45-60OMEGA的等效电阻。 等效电阻与输入/输出焊盘和第二电压源Vtt并联连接，以替代总线另一端的原始外部连接的端子电阻器rt2。 如果上拉使能线路没有通过电阻器连接到第一电压源Vdd，则场效应晶体管被切断，并且在源极和漏极端子之间产生无限等效电阻。 无限电阻在输入/输出焊盘和第二电压源Vtt之间并联连接。 无限等效电阻对总线另一端的任何外部连接的端子电阻rt2几乎没有影响。 因此，通过启用或禁用上拉使能线，制造商可以自由选择是否将总线的另一端的终端电阻rt2的输出功率节省。

公开(公告)号：US06554195B1

公开(公告)日：2003-04-29

申请号：US09422020

申请日：1999-10-20

Applicant: Nai-Shung Chang ,  Lie-Wen Chen ,  Ching-Fu Chuang ,  Chia-Hsing Yu

Inventor： Nai-Shung Chang ,  Lie-Wen Chen ,  Ching-Fu Chuang ,  Chia-Hsing Yu

IPC: G06K1906

CPC classification number: G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  H05K1/023 ,  H05K1/0262 ,  H05K1/117 ,  H05K1/141 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/10022 ,  H05K2201/10196 ,  H05K2201/10325 ,  H05K2201/10689

Abstract: A dual processor adapter card with a plurality of electrical pins for inserting into a processor slot on a mainboard by which the adapter card is electrically coupled to the mainboard. There is a first and a second processor socket on the adapter card for carrying a first and a second processor respectively. The first and the second processor socket each has a plurality of corresponding pins, a portion of the pins of the first and the second processor socket corresponds to a portion of the electrical pins. Corresponding pins are coupled together. Furthermore, each of the pins that act as a terminal lead in the first and the second processor socket is connected to a pull-up resistor, and the pull-up resistor is connected to a terminal voltage. In addition, a zero-delay buffer for synchronizing clock pulse signals and a voltage regulator for regulating a power voltage into a suitable working voltage are mounted on the adapter card and coupled to the first and the second processor socket respectively.

Abstract translation: 一种双处理器适配器卡，其具有多个电引脚，用于插入到主板上的处理器插槽中，通过该处理器插槽将适配器卡电耦合到主板。 适配器卡上有一个第一和第二个处理器插座，分别用于承载第一和第二处理器。 第一和第二处理器插座各自具有多个对应的引脚，第一和第二处理器插座的一部分引脚对应于电引脚的一部分。 相应的引脚耦合在一起。 此外，在第一和第二处理器插座中用作端子引线的每个引脚连接到上拉电阻器，并且上拉电阻器连接到端子电压。 此外，用于将时钟脉冲信号同步的零延迟缓冲器和用于将电源电压调节到合适工作电压的电压调节器分别安装在适配器卡上并分别耦合到第一和第二处理器插槽。

公开(公告)号：US06384346B1

公开(公告)日：2002-05-07

申请号：US09688037

申请日：2000-10-12

Applicant: Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho ,  Chia-Hsing Yuo ,  Shu-Hui Chen

Inventor： Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho ,  Chia-Hsing Yuo ,  Shu-Hui Chen

IPC: H01R909

CPC classification number: H05K7/1459 ,  H05K1/0216 ,  H05K2201/044 ,  H05K2201/09236

Abstract: A trace layout of a printed circuit board (PCB) is provided with a north bridge, at least a peripheral component interconnect (PCI) slot, and an accelerate graphics port (AGP) slot. The PCB includes at least a first trace layer and a second trace layer under the first trace layer. The AGP slot is mounted between the north bridge and the PCI slot. The PCB further includes a number of first traces, and a number of second traces. The first traces are used for connecting the north bridge to the PCI slot while the second traces are used to connect the north bridge to the AGP slot. Some of the first traces are on the second trace layer under the AGP slot, while the other of the first traces are on the first trace layer or the second trace layer and trace aside the AGP slot. Most of the second traces are on the first trace layer and the other of the second traces are on the second trace layer.

Abstract translation: 印刷电路板（PCB）的迹线布局提供有北桥，至少外围组件互连（PCI）插槽和加速图形端口（AGP）插槽。 PCB包括至少第一迹线层和第一迹线层下的第二迹线层。 AGP插槽安装在北桥和PCI插槽之间。 PCB还包括多个第一迹线和多个第二迹线。 第一条迹线用于将北桥连接到PCI插槽，而第二条路径用于将北桥连接到AGP插槽。 一些第一个迹线位于AGP插槽下的第二个跟踪层上，而第一个迹线中的另一个迹线位于第一个跟踪层或第二个跟踪层上，并跟踪AGP插槽。 大多数第二迹线位于第一迹线层上，而第二迹线中的另一条迹线位于第二迹线层上。

公开(公告)号：US6084425A

公开(公告)日：2000-07-04

申请号：US96057

申请日：1998-06-11

Applicant: Yuantsang Liaw ,  Ching-Fu Chuang ,  Nai-Shung Chang

Inventor： Yuantsang Liaw ,  Ching-Fu Chuang ,  Nai-Shung Chang

IPC: H03H7/40 ,  G01R19/00

CPC classification number: H03H7/40

Abstract: An impedance adjusting apparatus of a controlling chip on a computer mainboard. When a computer is turned on, BIOS automatically detects the actual usage of the memory sockets, and then sends corresponding control signals to adjust the impedance of the impedance adjusting apparatus for a better impedance matching between the controlling chip and the memory sockets. The signal reflection is dramatically reduced and the operation bandwidth is widened.

Abstract translation: 一种在计算机主板上的控制芯片的阻抗调节装置。 当计算机打开时，BIOS会自动检测内存插槽的实际使用情况，然后发送相应的控制信号，调整阻抗调整装置的阻抗，以便控制芯片和存储器插槽之间更好的阻抗匹配。 信号反射明显减少，工作带宽扩大。

公开(公告)号：US20140308947A1

公开(公告)日：2014-10-16

申请号：US13986215

申请日：2013-04-15

Applicant: Ching-Fu Chuang

Inventor： Ching-Fu Chuang

IPC: H04W4/22

CPC classification number: H04W4/90 ,  G01S13/56 ,  G08B13/2491

Abstract: The invention relates to a theft-prevention system for a mobile phone, primarily comprising a detection control system and a mobile phone, wherein the detection control system includes a microwave emitter, detection unit, and alarm tone, and a microwave reception unit is fit within the mobile phone, with said microwave reception unit being integrated into the mobile phone system; as a result, when the detection control system senses that someone is approaching or breaking in, it will emit a microwave signal to the microwave reception unit, while at the same time emitting an alarm tone, as well as activating the speaker of the mobile phone to notify the user indicates that someone has come within the set range, allowing the owner of the mobile phone to immediately act in response. The invention thus provides a more user-friendly, mobile phone-integrated theft-prevention system.

Abstract translation: 本发明涉及一种主要包括检测控制系统和移动电话的移动电话防盗系统，其中检测控制系统包括微波发射器，检测单元和报警音，微波接收单元适合于 所述移动电话将所述微波接收单元集成到所述移动电话系统中; 结果，当检测控制系统感测到某人正在接近或断开时，它将向微波接收单元发出微波信号，同时发出报警音，以及启动移动电话的扬声器 通知用户指示有人已经进入设定范围，允许手机的所有者立即作出响应。 因此，本发明提供了一种更加用户友好的移动电话集成的防盗系统。

公开(公告)号：US06970477B2

公开(公告)日：2005-11-29

申请号：US09683647

申请日：2002-01-29

Applicant: Ching-Fu Chuang ,  Chia-Hsin Chen

Inventor： Ching-Fu Chuang ,  Chia-Hsin Chen

IPC: H04L1/08 ,  H04L12/54

CPC classification number: H04L1/08

Abstract: A data transmission circuit has an internal circuit for providing data, a register electrically connected to the internal circuit for temporarily storing the data transmitted from the input internal circuit, and a control circuit for controlling operations of the data transmission circuit. If data inputted to the register is specific data, the internal circuit will repeatedly output the specific data to the register so as to prolong transmission time of the specific data.

Abstract translation: 数据传输电路具有用于提供数据的内部电路，电连接到内部电路的用于临时存储从输入内部电路发送的数据的寄存器和用于控制数据传输电路的操作的控制电路。 如果输入到寄存器的数据是特定数据，则内部电路将重复地将特定数据输出到寄存器，以便延长特定数据的传输时间。

公开(公告)号：US20140206312A1

公开(公告)日：2014-07-24

申请号：US13694920

申请日：2013-01-22

Applicant: Ching-Fu Chuang

Inventor： Ching-Fu Chuang

IPC: G08B13/22

CPC classification number: G08B13/1436 ,  G08B13/149 ,  G08B13/181

Abstract: This invention is a type of mobile telephone with anti-theft functionality, primarily a mobile telephone with a detection beam emission system inside. The detection beam emission system has a sensor module (e.g. an infrared or human detection device) and a drive unit, and once the anti-theft function is activated, when a person approaches within a certain distance of the place where the mobile phone is placed, it will activate the telephone to emit a sound to attract attention to the person approaching, thereby achieving better anti-theft functionality in a mobile phone in order to protect personal property.

Abstract translation: 本发明是一种具有防盗功​​能的移动电话，主要是内部具有检测光束发射系统的移动电话。 检测光束发射系统具有传感器模块（例如，红外线或人体检测装置）和驱动单元，并且一旦防盗功能被激活，当人接近放置移动电话的地方的一定距离内时 将激活电话发出声音，引起人们的关注，从而在移动电话中实现更好的防盗功能，以保护个人财产。

公开(公告)号：US6133755A

公开(公告)日：2000-10-17

申请号：US136751

申请日：1998-08-19

Applicant: Jincheng Huang ,  Yuantsang Liaw ,  Ching-Fu Chuang

Inventor： Jincheng Huang ,  Yuantsang Liaw ,  Ching-Fu Chuang

IPC: H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00361

Abstract: An input/output (I/O) buffer with reduced ring-back effect is provided. This I/O buffer is designed for a data transmission bus, such as a GTL+bus, for the transmission of a high-frequency and low-swing data signal. This I/O buffer is designed for the purpose of reducing the undesirable ring-back effect in the I/O buffer. The I/O buffer is characterized by the provision of a variable-resistance device that is connected between the system voltage and the input end of the I/O buffer. The system voltage is set to be equal in magnitude to the high-voltage logic state of the data signal received by the I/O buffer from the data transmission bus. When the input data signal is higher in magnitude than a preset reference voltage, i.e., at the high-voltage logic state, the variable-resistance device is switched to a low resistance value; on the other hand, when the data signal is lower in magnitude than the reference voltage, the variable-resistance device is switched to a near-infinity resistance value. In both cases, no current will flow through the variable-resistance device. This feature can help reduce the ring-back effect in the I/O buffer and also allows the benefits of low power consumption and reduced layout area on the circuit board as compared to the prior art.

Abstract translation: 提供了具有降低回铃效果的输入/输出（I / O）缓冲器。 该I / O缓冲器被设计用于数据传输总线，例如GTL +总线，用于传输高频和低频数据信号。 该I / O缓冲器是为了减少I / O缓冲器中不良的环回效应而设计的。 I / O缓冲器的特征在于提供连接在系统电压和I / O缓冲器的输入端之间的可变电阻器件。 将系统电压设置为与数据传输总线由I / O缓冲器接收的数据信号的高电压逻辑状态相等。 当输入数据信号的幅度高于预设参考电压即高电压逻辑状态时，可变电阻器件切换到低电阻值; 另一方面，当数据信号的幅度低于参考电压时，可变电阻器件被切换到近无限电阻值。 在这两种情况下，没有电流流过可变电阻器件。 与现有技术相比，该功能可以帮助减少I / O缓冲区中的环回效应，并且还可以实现电路板上低功耗和减少布局面积的优点。

公开(公告)号：US6031752A

公开(公告)日：2000-02-29

申请号：US111034

申请日：1998-07-07

Applicant: Jiin Lai ,  Ching-Fu Chuang

Inventor： Jiin Lai ,  Ching-Fu Chuang

IPC: G11C5/00 ,  G11C5/02

CPC classification number: G06F13/409

Abstract: An installation inside a memory slot for providing a constant loading to an external signaling line with or without the insertion of a memory module into a memory slot. The installation operates by supplying a load element whose loading effect is roughly equivalent to the loading effect of a memory module when no memory module is plugged, and disconnecting the load element internally when a memory module is plugged into the memory slot. Hence, a constant loading is provided to the external signaling line no matter a memory module is plugged or not, and so signal quality and integrity of the signaling line can be maintained.

Abstract translation: 存储器插槽内部的安装，用于通过或不将存储器模块插入到存储器插槽中来向外部信号线提供恒定的加载。 当没有存储器模块插入时，通过提供负载效应大致等于存储器模块的负载效应的负载元件，并且当存储器模块插入到存储器插槽中时将该负载元件断开。 因此，无论存储器模块是否被插入，都向外部信号线提供恒定的负载，因此可以保持信号线的信号质量和完整性。