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    METHOD FOR FORMING VOID-FREE DIELECTRIC LAYER
    1.
    发明申请
    METHOD FOR FORMING VOID-FREE DIELECTRIC LAYER 有权
    形成无电介质层的方法

    公开(公告)号：US20130109151A1

    公开(公告)日：2013-05-02

    申请号：US13281459

    申请日：2011-10-26

    申请人： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

    发明人： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76232

    摘要： A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.

    摘要翻译： 公开了一种形成没有空隙的电介质层的方法。 首先，提供基板，包括凹部的第一应力层，设置在第一应力层上并覆盖凹部的第二应力层和嵌入凹部中的图案化光致抗蚀剂。 第二，执行第一蚀刻步骤以完全去除光致抗蚀剂，使得剩余的第二应力层形成邻近凹部的至少一个突起。 然后，在不暴露的情况下形成修整光致抗蚀剂以填充凹部并覆盖突起。 然后，进行修整蚀刻步骤以消除突起并且顺利地移除修整光致抗蚀剂。

    Method for forming void-free dielectric layer
    2.
    发明授权
    Method for forming void-free dielectric layer 有权
    无空隙电介质层形成方法

    公开(公告)号：US08691659B2

    公开(公告)日：2014-04-08

    申请号：US13281459

    申请日：2011-10-26

    申请人： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

    发明人： Ching-Pin Hsu ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Chieh-Te Chen ,  Feng-Yi Chang ,  Shang-Yuan Tsai ,  Li-Chiang Chen

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76232

    摘要： A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.

    摘要翻译： 公开了一种形成没有空隙的电介质层的方法。 首先，提供基板，包括凹部的第一应力层，设置在第一应力层上并覆盖凹部的第二应力层和嵌入凹部中的图案化光致抗蚀剂。 第二，执行第一蚀刻步骤以完全去除光致抗蚀剂，使得剩余的第二应力层形成邻近凹部的至少一个突起。 然后，在不暴露的情况下形成修整光致抗蚀剂以填充凹部并覆盖突起。 然后，进行修整蚀刻步骤以消除突起并且顺利地移除修整光致抗蚀剂。

    Method for fabricating CMOS transistor
    4.
    发明授权
    Method for fabricating CMOS transistor 有权
    制造CMOS晶体管的方法

    公开(公告)号：US08252650B1

    公开(公告)日：2012-08-28

    申请号：US13092151

    申请日：2011-04-22

    申请人： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

    发明人： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823864

    摘要： A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.

    摘要翻译： 一种用于制造MOS晶体管的方法包括以下步骤：在蚀刻停止层和基板的边界区域处的第一应力层上重叠第二应力层; 在所述第一应力层和所述第二应力层上形成介电层; 执行第一蚀刻工艺以部分去除所述电介质层以暴露所述边界区域处的所述第二应力层的一部分; 执行第二蚀刻工艺以部分地去除第二应力层的暴露部分以暴露蚀刻停止层; 执行第三蚀刻工艺以部分地去除用于在边界区域露出第一应力层的蚀刻停止层的暴露部分; 并且执行第四蚀刻工艺部分地去除第一应力层的暴露部分。

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    5.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
    半导体器件的制造方法

    公开(公告)号：US20140073104A1

    公开(公告)日：2014-03-13

    申请号：US13609213

    申请日：2012-09-10

    申请人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Shang-Yuan Tsai

    发明人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Shang-Yuan Tsai

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76816 ,  H01L21/31144 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole.

    摘要翻译： 在本发明中公开了一种半导体器件的制造方法。 首先，在衬底上形成至少一个栅极结构和多个源极/漏极区域，然后在衬底上形成电介质层，在电介质层中分别在栅极上形成第一接触孔和第二接触孔 结构和源极/漏极区，以及在电介质层中形成第三接触孔，其中第三接触孔与第一接触孔和第二接触孔重叠。

    Manufacturing method of semiconductor device
    7.
    发明授权
    Manufacturing method of semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US09196524B2

    公开(公告)日：2015-11-24

    申请号：US13609213

    申请日：2012-09-10

    申请人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Shang-Yuan Tsai

    发明人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Feng-Yi Chang ,  Shang-Yuan Tsai

    IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/311

    CPC分类号： H01L21/76816 ,  H01L21/31144 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole.

    摘要翻译： 在本发明中公开了一种半导体器件的制造方法。 首先，在衬底上形成至少一个栅极结构和多个源极/漏极区域，然后在衬底上形成电介质层，在电介质层中分别在栅极上形成第一接触孔和第二接触孔 结构和源极/漏极区，以及在电介质层中形成第三接触孔，其中第三接触孔与第一接触孔和第二接触孔重叠。

    Semiconductor structure and process thereof
    8.
    发明授权
    Semiconductor structure and process thereof 有权
    半导体结构及其工艺

    公开(公告)号：US08952392B2

    公开(公告)日：2015-02-10

    申请号：US13369260

    申请日：2012-02-08

    申请人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

    发明人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

    IPC分类号： H01L29/15 ,  H01L21/336

    CPC分类号： H01L28/20 ,  H01L21/76897 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

    摘要： A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.

    摘要翻译： 半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。 衬底具有隔离结构。 抗蚀剂层位于隔离结构上。 介电材料位于抗蚀剂层上。 两个U形金属层位于电介质材料的两侧和抗蚀剂层上。 两个金属分别位于两个U形金属层上。 以这种方式提供了用于形成所述半导体结构的半导体工艺。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    9.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
    半导体结构及其工艺

    公开(公告)号：US20130200393A1

    公开(公告)日：2013-08-08

    申请号：US13369260

    申请日：2012-02-08

    申请人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

    发明人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

    IPC分类号： H01L29/16 ,  H01L21/28

    CPC分类号： H01L28/20 ,  H01L21/76897 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

    摘要： A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.

    摘要翻译： 半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。 衬底具有隔离结构。 抗蚀剂层位于隔离结构上。 介电材料位于抗蚀剂层上。 两个U形金属层位于电介质材料的两侧和抗蚀剂层上。 两个金属分别位于两个U形金属层上。 以这种方式提供了用于形成所述半导体结构的半导体工艺。

    Semiconductor device and fabrication method thereof
    10.
    发明授权
    Semiconductor device and fabrication method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US08633549B2

    公开(公告)日：2014-01-21

    申请号：US13267068

    申请日：2011-10-06

    申请人： Chieh-Te Chen ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Yi-Po Lin

    发明人： Chieh-Te Chen ,  Shih-Fang Tzou ,  Jiunn-Hsiung Liao ,  Yi-Po Lin

    IPC分类号： H01L27/11 ,  H01L21/8234 ,  H01L21/8244

    CPC分类号： H01L21/28079 ,  H01L21/027 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/8232 ,  H01L27/0629

    摘要： A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.

    摘要翻译： 半导体器件包括金属栅电极，无源器件和硬掩模层。 无源器件具有多晶硅元件层。 硬掩模层设置在金属栅电极和无源电极上，并且具有彼此基本共面的第一开口和第二开口，其中金属栅极电极和多晶硅元件层分别经由第一开口暴露， 第二个开口 并且第一开口和金属栅电极之间的距离基本上小于第二开口和多晶硅元件层之间的距离。