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14 条记录 (耗时 0.034 秒)

    Method for fabricating CMOS transistor
    2.
    发明授权
    Method for fabricating CMOS transistor 有权
    制造CMOS晶体管的方法

    公开(公告)号：US08252650B1

    公开(公告)日：2012-08-28

    申请号：US13092151

    申请日：2011-04-22

    申请人： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

    发明人： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823864

    摘要： A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.

    摘要翻译： 一种用于制造MOS晶体管的方法包括以下步骤：在蚀刻停止层和基板的边界区域处的第一应力层上重叠第二应力层; 在所述第一应力层和所述第二应力层上形成介电层; 执行第一蚀刻工艺以部分去除所述电介质层以暴露所述边界区域处的所述第二应力层的一部分; 执行第二蚀刻工艺以部分地去除第二应力层的暴露部分以暴露蚀刻停止层; 执行第三蚀刻工艺以部分地去除用于在边界区域露出第一应力层的蚀刻停止层的暴露部分; 并且执行第四蚀刻工艺部分地去除第一应力层的暴露部分。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    6.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
    半导体结构及其工艺

    公开(公告)号：US20130200393A1

    公开(公告)日：2013-08-08

    申请号：US13369260

    申请日：2012-02-08

    申请人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

    发明人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

    IPC分类号： H01L29/16 ,  H01L21/28

    CPC分类号： H01L28/20 ,  H01L21/76897 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

    摘要： A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.

    摘要翻译： 半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。 衬底具有隔离结构。 抗蚀剂层位于隔离结构上。 介电材料位于抗蚀剂层上。 两个U形金属层位于电介质材料的两侧和抗蚀剂层上。 两个金属分别位于两个U形金属层上。 以这种方式提供了用于形成所述半导体结构的半导体工艺。

    Semiconductor structure and process thereof
    7.
    发明授权
    Semiconductor structure and process thereof 有权
    半导体结构及其工艺

    公开(公告)号：US08952392B2

    公开(公告)日：2015-02-10

    申请号：US13369260

    申请日：2012-02-08

    申请人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

    发明人： Chieh-Te Chen ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shui-Yen Lu ,  Li-Chiang Chen

    IPC分类号： H01L29/15 ,  H01L21/336

    CPC分类号： H01L28/20 ,  H01L21/76897 ,  H01L27/0629 ,  H01L28/24 ,  H01L29/66545

    摘要： A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.

    摘要翻译： 半导体结构包括基板，抗蚀剂层，电介质材料，两个U形金属层和两种金属。 衬底具有隔离结构。 抗蚀剂层位于隔离结构上。 介电材料位于抗蚀剂层上。 两个U形金属层位于电介质材料的两侧和抗蚀剂层上。 两个金属分别位于两个U形金属层上。 以这种方式提供了用于形成所述半导体结构的半导体工艺。

    Semiconductor process
    9.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US08835243B2

    公开(公告)日：2014-09-16

    申请号：US13463819

    申请日：2012-05-04

    申请人： Tzung-I Tsai ,  Shui-Yen Lu

    发明人： Tzung-I Tsai ,  Shui-Yen Lu

    IPC分类号： H01L21/8248

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L27/092

    摘要： A semiconductor process includes the following steps. A first structure and a second structure are formed on a substrate. An oxide layer is entirely formed to cover the first structure and the second structure. A nitride layer is formed to entirely cover the oxide layer. A dry etching process is performed to remove a part of the nitride layer on the first structure. A wet etching process is performed to entirely remove the nitride layer and the oxide layer on the first structure and the second structure.

    摘要翻译： 半导体工艺包括以下步骤。 在基板上形成第一结构和第二结构。 完全形成氧化物层以覆盖第一结构和第二结构。 形成氮化物层以完全覆盖氧化物层。 执行干蚀刻处理以去除第一结构上的氮化物层的一部分。 执行湿蚀刻工艺以完全去除第一结构和第二结构上的氮化物层和氧化物层。