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1.发明授权High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs 失效用于混合定向技术的高性能PFET接头，用于数字CMOS VLSI设计中的漏电减少公开(公告)号：US07274217B2
公开(公告)日：2007-09-25
申请号：US11100883
申请日：2005-04-07
IPC分类号： H01L23/62 , H03K19/094
CPC分类号： H03K19/0016 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： Discloses are CMOS circuit designs that combine MTCMOS and hybrid orientation technology to achieve the dual objectives of high performance and low standby leakage power. The invention utilizes novel combinations of a thick-oxide high-VTH PFET header with various gate- and body-biased schemes in HOT technology to significantly reduce the performance penalty associated with conventional PFET headers. A first embodiment of the invention provides a HOT-B high-VTH thick oxide bulk PFET header scheme. This header scheme can be expanded by application of a positive gate bias VPOS (VPOS>VDD) to the HOT-B PFET header during standby mode and a negative gate bias VNEG (VNEG
摘要翻译： 公开了结合MTCMOS和混合定向技术的CMOS电路设计，以实现高性能和低待机泄漏功率的双重目标。 本发明利用HOT技术中的厚氧化物高VTH PFET集线器的新型组合与各种栅极和体偏置方案，以显着降低与常规PFET集管相关的性能损失。 本发明的第一实施例提供了一种HOT-B高VTH厚氧化物体PFET头方案。 可以通过在待机模式期间将正栅极偏置VPOS（VPOS> VDD）施加到HOT-B PFET头并且在活动模式下使用负栅极偏置VNEG（VNEG
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2.发明授权Tri-state dynamic body charge modulation for sensing devices in SOI RAM applications 失效用于SOI RAM应用中感测器件的三态动态电荷调制公开(公告)号：US06373281B1
公开(公告)日：2002-04-16
申请号：US09767218
申请日：2001-01-22
IPC分类号： H03K1900
CPC分类号： G11C7/065
摘要： A method and apparatus are provided for tri-state dynamic body charge modulation for sensing devices in silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) applications. A sense amplifier includes a silicon-on-insulator (SOI) field effect transistor. A tri-state body charge modulation circuit is coupled to a body of the silicon-on-insulator (SOI) field effect transistor. The body charge modulation circuit provides a high body bias preparatory state; a floating body state and a low body bias stand-by state enabling high performance operation, good matching characteristics, and low stand-by leakage suitable for low-power applications. The tri-state body charge modulation circuit includes a P-channel field effect transistor (PFET) and an N-channel field effect transistor (NFET) connected between a high voltage potential and ground. The junction of the series connected PFET and NFET is coupled to the SOI FET body for providing a charging path to a high power supply voltage rail and a discharging path to ground and a high impedance state.
摘要翻译： 提供了一种用于感测绝缘体上硅（SOI）互补金属氧化物半导体（CMOS）应用中的器件的三态动态电荷调制的方法和装置。 读出放大器包括绝缘体上硅（SOI）场效应晶体管。 三态体电荷调制电路耦合到绝缘体上硅（SOI）场效应晶体管的主体。 身体电荷调制电路提供高体偏置准备状态; 浮体状态和低体态偏置待机状态，可实现高性能运行，良好的匹配特性，适用于低功率应用的低待机泄漏。 三态体电荷调制电路包括连接在高压电位和地之间的P沟道场效应晶体管（PFET）和N沟道场效应晶体管（NFET）。 串联连接的PFET和NFET的结连接到SOI FET体，用于提供到高电源电压轨的充电路径和到地的放电路径和高阻抗状态。
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3.发明申请Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 有权使用非对称双栅极器件中二极管电压的独立控制改变电源电压或参考电压的方法和装置公开(公告)号：US20090302929A1
公开(公告)日：2009-12-10
申请号：US12511658
申请日：2009-07-29
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译： 提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。 提供由电源电压和参考电压中的一个或多个控制的集成电路。 集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。 独立控制可以包括例如背栅偏置。 独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。
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4.发明授权High-density logic techniques with reduced-stack multi-gate field effect transistors 有权具有减少堆叠多栅极场效应晶体管的高密度逻辑技术公开(公告)号：US07382162B2
公开(公告)日：2008-06-03
申请号：US11181954
申请日：2005-07-14
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K19/0948 , H01L29/78648
摘要： Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
摘要翻译： 提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。 只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。 可以减小电路面积，提高性能。
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5.发明申请HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD EFFECT TRANSISTORS 有权具有减少堆叠多栅极场效应晶体管的高密度逻辑技术公开(公告)号：US20100026346A1
公开(公告)日：2010-02-04
申请号：US12102097
申请日：2008-04-14
IPC分类号： H03K19/094 , G06F17/50
CPC分类号： H03K19/0948 , H01L29/78648
摘要： Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
摘要翻译： 提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。 只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。 可以减小电路面积，提高性能。
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公开(公告)号：US07177177B2
公开(公告)日：2007-02-13
申请号：US11100893
申请日：2005-04-07
申请人： Ching-Te Kent Chuang , Jae-Joon Kim , Keunwoo Kim
发明人： Ching-Te Kent Chuang , Jae-Joon Kim , Keunwoo Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An eight transistor static random access memory (SRAM)device includes first and second inverters, a first bit line, a first complement bit line, a pair of write access transistors, and a pair of read access transistors. Each of the first and second inverters includes a respective pair of transistors, and has a respective data node. Each of a first and a second of the access transistors has a source, a drain, a front gate, and a back gate. The first access transistor is coupled to the first bit line, and the second access transistor is coupled to the first complement bit line. The back gate of the first access transistor is coupled to the data node of the first inverter; and the back gate of the second access transistor is coupled to the data node of the second inverter. This increases the difference between the threshold voltages of the first and second access transistors.
摘要翻译： 八晶体管静态随机存取存储器（SRAM）器件包括第一和第二反相器，第一位线，第一补码位线，一对写存取晶体管和一对读存取晶体管。 第一和第二反相器中的每一个包括相应的晶体管对，并具有相应的数据节点。 第一和第二存取晶体管中的每一个具有源极，漏极，前栅极和后栅极。 第一存取晶体管耦合到第一位线，第二存取晶体管耦合到第一补码位线。 第一存取晶体管的背栅极耦合到第一反相器的数据节点; 并且第二存取晶体管的背栅极耦合到第二反相器的数据节点。 这增加了第一和第二存取晶体管的阈值电压之间的差异。
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公开(公告)号：US5017990A
公开(公告)日：1991-05-21
申请号：US445251
申请日：1989-12-01
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/732
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/732
摘要： The invention relates to a bipolar transistor structure which includes a layer of semiconductor material having a single crystal raised base, a single crystal or polycrystalline emitter and adjacent polycrystalline regions which provide an electrical connection to the emitter. The invention also relates to the method of fabricating such a structure and includes the step of depositing a conformal layer of semiconductor material of one conductivity type over a region of opposite conductivity and over insulation such that single crystal and polycrystalline regions form over single crystal material and insulation, respectively. In a subsequent step, a layer of opposite conductivity type semiconductor material is deposited on the first layer forming single crystal or polycrystalline material over single crystal and polycrystalline material over polycrystalline. Then, in a final step, the structure is subjected to an out-diffusion step which simultaneously forms a single crystal emitter region of opposite conductivity type, a p-n junction in the one conductivity type single crystal region and regions of opposite conductivity type which act as an interconnection to the emitter region.
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8.发明授权High-density logic techniques with reduced-stack multi-gate field effect transistors 有权具有减少堆叠多栅极场效应晶体管的高密度逻辑技术公开(公告)号：US08030971B2
公开(公告)日：2011-10-04
申请号：US12102097
申请日：2008-04-14
IPC分类号： H03K19/20 , H03K19/094
CPC分类号： H03K19/0948 , H01L29/78648
摘要： Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.
摘要翻译： 提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。 只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。 可以减小电路面积，提高性能。
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公开(公告)号：US20090303778A1
公开(公告)日：2009-12-10
申请号：US12511666
申请日：2009-07-29
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
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公开(公告)号：US06448830B1
公开(公告)日：2002-09-10
申请号：US10007854
申请日：2001-11-05
IPC分类号： H03K3037
CPC分类号： H03K3/3565
摘要： A tri-state Schmitt trigger inverting device having multiple tri-state controller switching devices between a conventional voltage mode Schmitt trigger its voltage supply rails. When an enabling signal to the tri-state controller switching devices is set to a first level, the tri-state Schmitt trigger functions as a standard logic inverter. When a complementary enabling signal is received at the tri-state controller switching devices, the connections to the high voltage rail and low voltage rail of the tri-state Schmitt trigger are turned off, and the output of the tri-state Schmitt trigger is a high impedance. Thus, the device is a single stage tri-state Schmitt inverter having optimal hysteresis characteristics with minimal power consumption.
摘要翻译： 在常规电压模式施密特触发其电压供应轨之间的具有多个三态控制器开关装置的三态施密特触发器反相装置。 当三态控制器开关器件的使能信号被设置为第一电平时，三态施密特触发器用作标准逻辑反相器。 当在三态控制器开关器件处接收到补充使能信号时，三态施密特触发器的与高电压轨和低电压轨的连接被关闭，并且三态施密特触发器的输出为 高阻抗。 因此，器件是具有最小功耗的最佳滞后特性的单级三态施密特逆变器。
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