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    Chip scale package with flip chip interconnect
    1.
    发明申请
    Chip scale package with flip chip interconnect 有权
    芯片级封装，带倒装芯片互连

    公开(公告)号：US20020151189A1

    公开(公告)日：2002-10-17

    申请号：US10081491

    申请日：2002-02-22

    Applicant: ChipPAC, Inc.

    Inventor： Rajendra Pendse ,  Nazir Ahmad ,  Andrea Chen ,  Kyung-Moon Kim ,  Young-Do Kweon ,  Samuel Tam

    IPC: H01L023/48 ,  H01L021/56

    CPC classification number: H01L21/563 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099

    Abstract: A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as 70 micrometers pitch. Also, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern in relation to the positions of the second level interconnections between the package and the printed circuit board. According to this aspect of the invention, the coefficient of thermal expansion and the compliancy of the package structure in the regions overlying the second level connections can be tailored to reduce potentially damaging propagation of stress generated in the second level connections on the package to features on the integrated circuit chip, and thereby extending the long-term reliability of the package and of the interconnects.

    Abstract translation: 通过用于连接集成电路芯片上的输入/输出焊盘和封装衬底的固态键合技术来形成倒装芯片封装。 固态键合技术涉及金属表面的直接配合，并且不使用任何颗粒状导电材料。 因此，与ACA或ICA微粒互连相比，连接能够承载非常高的电流，并且显示良好的长期可靠性。 此外，固态键合技术不需要任何互连材料的熔化或流动。 因此，连接可以以非常精细的几何形状形成，通常低至70微米间距。 此外，集成电路芯片的表面和封装基板的下表面之间的空间填充有图案化的粘合剂结构，其由一个或多个粘合材料组成，所述粘合材料以指定图案相对于 封装和印刷电路板之间的第二级互连。 根据本发明的这个方面，覆盖在二级连接区域上的封装结构的热膨胀系数和符合性可以被定制，以减少在包装上的第二层连接中产生的应力的潜在的破坏性传播到 集成电路芯片，从而延长封装和互连的长期可靠性。

    Chip scale package with flip chip interconnect
    2.
    发明申请
    Chip scale package with flip chip interconnect 审中-公开
    芯片级封装，带倒装芯片互连

    公开(公告)号：US20040222440A1

    公开(公告)日：2004-11-11

    申请号：US10838639

    申请日：2004-05-04

    Applicant: ChipPAC, Inc

    Inventor： Rajendra Pendse ,  Nazir Ahmad ,  Andrea Chen ,  Kyung-Moon Kim ,  Young Do Kweon ,  Samuel Tam

    IPC: H01L027/10

    CPC classification number: H01L21/563 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099

    Abstract: A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as 70 micrometers pitch. Also, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern relation to the positions of the second level interconnections between the package and the printed circuit board. According to this aspect of the invention, the coefficient of thermal expansion and the compliancy of the package structure in the regions overlying the second level connections can be tailored to reduce potentially damaging propagation of stress generated in the second level connections on the package to features on the integrated circuit chip, and thereby extending the long-term reliability of the package and of the interconnects.

    Abstract translation: 通过用于连接集成电路芯片上的输入/输出焊盘和封装衬底的固态键合技术来形成倒装芯片封装。 固态键合技术涉及金属表面的直接配合，并且不使用任何颗粒状导电材料。 因此，与ACA或ICA微粒互连相比，连接能够承载非常高的电流，并且显示良好的长期可靠性。 此外，固态键合技术不需要任何互连材料的熔化或流动。 因此，连接可以以非常精细的几何形状形成，通常低至70微米间距。 此外，集成电路芯片的表面和封装衬底的下表面之间的空间填充有图案化的粘合剂结构，其由一个或多个粘合材料组成，所述粘合剂材料以与第二个 封装和印刷电路板之间的高级互连。 根据本发明的这个方面，覆盖在二级连接区域上的封装结构的热膨胀系数和符合性可以被定制，以减少在包装上的第二层连接中产生的应力的潜在的破坏性传播到 集成电路芯片，从而延长封装和互连的长期可靠性。

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