公开(公告)号：US20020151189A1

公开(公告)日：2002-10-17

申请号：US10081491

申请日：2002-02-22

Applicant: ChipPAC, Inc.

Inventor： Rajendra Pendse ,  Nazir Ahmad ,  Andrea Chen ,  Kyung-Moon Kim ,  Young-Do Kweon ,  Samuel Tam

IPC: H01L023/48 ,  H01L021/56

CPC classification number: H01L21/563 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099

Abstract: A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as 70 micrometers pitch. Also, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern in relation to the positions of the second level interconnections between the package and the printed circuit board. According to this aspect of the invention, the coefficient of thermal expansion and the compliancy of the package structure in the regions overlying the second level connections can be tailored to reduce potentially damaging propagation of stress generated in the second level connections on the package to features on the integrated circuit chip, and thereby extending the long-term reliability of the package and of the interconnects.

Abstract translation: 通过用于连接集成电路芯片上的输入/输出焊盘和封装衬底的固态键合技术来形成倒装芯片封装。 固态键合技术涉及金属表面的直接配合，并且不使用任何颗粒状导电材料。 因此，与ACA或ICA微粒互连相比，连接能够承载非常高的电流，并且显示良好的长期可靠性。 此外，固态键合技术不需要任何互连材料的熔化或流动。 因此，连接可以以非常精细的几何形状形成，通常低至70微米间距。 此外，集成电路芯片的表面和封装基板的下表面之间的空间填充有图案化的粘合剂结构，其由一个或多个粘合材料组成，所述粘合材料以指定图案相对于 封装和印刷电路板之间的第二级互连。 根据本发明的这个方面，覆盖在二级连接区域上的封装结构的热膨胀系数和符合性可以被定制，以减少在包装上的第二层连接中产生的应力的潜在的破坏性传播到 集成电路芯片，从而延长封装和互连的长期可靠性。

公开(公告)号：US20020151228A1

公开(公告)日：2002-10-17

申请号：US10080384

申请日：2002-02-22

Applicant: ChipPAC, Inc.

Inventor： Young-Do Kweon ,  Rajendra Pendse ,  Nazir Ahmad ,  Kyung-Moon Kim

IPC: H01L029/41 ,  H01L029/40 ,  H01R013/03

CPC classification number: H01L24/12 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/1134 ,  H01L2224/11831 ,  H01L2224/1184 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool. Also, a method for forming an interconnect between a first member and a second member of an electronic package includes providing one of the members with the stud bumps of the invention and then bringing the corresponding bumps and pads together in a bonding process, the compliance of the stems portions of the bumps accommodating the variance from coplanarity of the pad surfaces.

Abstract translation: 用于一对构件之间的电互连的柱形凸块结构包括基部和杆部。 基座部分固定在要互连的一对构件之一（例如集成电路芯片）中的垫或轨迹中，并且杆端构造成接触另一构件上的金属垫（例如印刷电路 板）完成互连。 根据本发明，杆端被截断以形成横向平面，并且杆比基座更顺从。 此外，在接触表面上形成柱形凸块的方法包括在表面上形成凸起基部，从基部的顶部抽出大致圆锥形的尾部，并且使尾部截断以形成具有平面横向 并且具有从基部的顶部到顶表面的长度。 在一些实施例中，至少螺柱凸块的尾部部分使用引线接合工具形成。 此外，用于在电子封装的第一部件和第二部件之间形成互连的方法包括：使部件中的一个部件具有本发明的螺柱凸块，然后在相互粘接过程中将相应的凸块和焊盘接合在一起， 凸块的杆部分容纳与焊盘表面的共面性的差异。