公开(公告)号：US5991903A

公开(公告)日：1999-11-23

申请号：US909300

申请日：1997-08-11

申请人： Choong-Sun Shin ,  Yong-Sik Seok

发明人： Choong-Sun Shin ,  Yong-Sik Seok

IPC分类号： G01R31/28 ,  G11C29/26 ,  G11C29/34 ,  G11C29/38 ,  H01L21/66 ,  G11C29/00 ,  G06F7/02

CPC分类号： G11C29/26 ,  G11C29/38

摘要： A novel parallel bit test circuit is provided to test a semiconductor memory device which comprises a number of memory cell arrays each having a plurality of memory cells, a word line provided in each memory cell array to commonly connect with the plurality of memory cells, and a plurality of I/O (input/output) lines respectively connected with the plurality of memory cells of each memory cell array. The parallel bit test circuit for testing the plurality of memory cells in parallel bits comprises a comparator for comparing the data of the memory cells with an externally input data to produce a test signal applied to a data I/O terminal.

摘要翻译： 提供了一种新颖的并行比特测试电路来测试半导体存储器件，其包括多个存储单元阵列，每个存储单元阵列具有多个存储器单元，每个存储单元阵列中提供的字线与多个存储器单元共同连接;以及 分别与每个存储单元阵列的多个存储单元连接的多个I / O（输入/输出）线。 用于以并行比特测试多个存储单元的并行比特测试电路包括比较器，用于将存储器单元的数据与外部输入数据进行比较，以产生施加到数据I / O端子的测试信号。

公开(公告)号：US5657280A

公开(公告)日：1997-08-12

申请号：US580737

申请日：1995-12-29

申请人： Choong-Sun Shin ,  Yong-Sik Seok

发明人： Choong-Sun Shin ,  Yong-Sik Seok

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/785

摘要： A defective cell repairing circuit for repairing a defective cell in a packaged semiconductor memory device enables repair mode operations for mapping an address of a detected defective cell to a redundant cell. The address of the defective cell is programmed by selectively cutting fuses corresponding to each bit of the defective cell address. The defective cell address programming operation uses input terminals on the packaged semiconductor memory device which are used for address signals in a normal operation mode, so that no additional pins are required. Repair mode operations are prevented after the repair mode is completed. Thereafter, an external address supplied to the semiconductor memory device is compared with the programmed defective cell address determined by the state of the fuses, and a redundant cell is selected if the two addresses correspond.

摘要翻译： 用于修复封装的半导体存储器件中的故障单元的缺陷单元修复电路能够进行用于将检测到的缺陷单元的地址映射到冗余单元的修复模式操作。 通过选择性地切割与缺陷单元地址的每个位对应的熔丝来编程有缺陷单元的地址。 缺陷单元地址编程操作使用在正常操作模式下用于地址信号的封装半导体存储器件上的输入端子，从而不需要额外的引脚。 修复模式完成后，可以防止修复模式操作。 此后，将提供给半导体存储器件的外部地址与由保险丝的状态确定的编程故障单元地址进行比较，并且如果两个地址对应，则选择冗余单元。

公开(公告)号：US5396465A

公开(公告)日：1995-03-07

申请号：US156779

申请日：1993-11-24

申请人： Seung-Cheol Oh ,  Yong-Sik Seok

发明人： Seung-Cheol Oh ,  Yong-Sik Seok

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C29/50 ,  G11C11/401

摘要： A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.

摘要翻译： 半导体存储器件具有设置在公共位读出放大器和存储器阵列之间的相邻存储器阵列和隔离晶体管。 根据本发明的隔离控制电路在老化操作模式期间产生电源电压Vcc（而不是升压电压Vpp），从而防止隔离晶体管的栅极氧化层被破坏或劣化。

公开(公告)号：US5325334A

公开(公告)日：1994-06-28

申请号：US14305

申请日：1993-02-05

申请人： Jae-Gu Roh ,  Yong-Sik Seok

发明人： Jae-Gu Roh ,  Yong-Sik Seok

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/808

摘要： A column redundancy circuit for a semiconductor memory device, e.g., a DRAM, which includes a normal memory array comprised of a plurality of memory blocks each comprised of a matrix of rows and columns of memory cells, with at least two of the memory blocks sharing common columns, and with at least one of the columns being defective, in the sense of being connected to at least one memory cell which has been determined to be defective. The column redundancy circuit includes a plurality of redundant columns, block selection control circuit which is programmed to generate a first output signal in response to receipt of a memory block address signal corresponding to one or more of the memory blocks which contain the defective column, a column address decoder which is programmed to generate a second output signal in response to receipt of both the first output signal and a column address signal corresponding to the defective column, and, a redundant column driver circuit which is responsive to the second output signal for activating a predetermined one of the redundant columns, to thereby repair the defective column. In a preferred embodiment, the block selection control circuit and the column address decoder each include a plurality of fuses and are each programmed by means of a selected one or more of their fuses being blown, e.g., by use of a laser.

摘要翻译： 一种用于半导体存储器件（例如DRAM）的列冗余电路，其包括由多个存储块构成的正常存储器阵列，每个存储器块由行和列的存储器单元组成，其中至少两个存储器块共享 公共列，并且至少一个列是有缺陷的，在连接到被确定为有缺陷的至少一个存储单元的意义上。 列冗余电路包括多个冗余列，块选择控制电路被编程为响应于接收到与包含缺陷列的一个或多个存储器块相对应的存储器块地址信号而产生第一输出信号， 列地址解码器，其被编程为响应于接收到与缺陷列对应的第一输出信号和列地址信号两者而产生第二输出信号;以及冗余列驱动器电路，其响应于第二输出信号用于激活 冗余列中的预定的一个，从而修复有缺陷的列。 在优选实施例中，块选择控制电路和列地址解码器各自包括多个保险丝，并且各自通过例如通过使用激光而被熔断的所选择的一个或多个保险丝进行编程。

公开(公告)号：US5319605A

公开(公告)日：1994-06-07

申请号：US726180

申请日：1991-07-05

申请人： Dong-Seon Min ,  Kyoung-Yeol Min ,  Dong-Su Jeon ,  Yong-Sik Seok

发明人： Dong-Seon Min ,  Kyoung-Yeol Min ,  Dong-Su Jeon ,  Yong-Sik Seok

IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/14

摘要： An arrangement of a word line driver stage for semiconductor memory device is disclosed. The present invention is characterized in that a word line driver stages are into several sub-stages WD11-WD51 within a memory cell array, and each word line extending from a first one or a second one of the sub-stages is alternatively coupled to the sub-stage adjacent thereto. Thus this arrangement is capable of reducing the signal transmission delay and eliminating the adverse factor in the current critical design rule and layout.

摘要翻译： 公开了一种用于半导体存储器件的字线驱动器级的布置。 本发明的特征在于，字线驱动器级在存储单元阵列内分成几个子级WD11-WD51，并且从第一级或第二级子级延伸的每条字线交替耦合到 与其相邻的子级。 因此，这种布置能够减少信号传输延迟并消除当前关键设计规则和布局中的不利因素。

公开(公告)号：US5255234A

公开(公告)日：1993-10-19

申请号：US674387

申请日：1991-03-25

申请人： Yong-Sik Seok

发明人： Yong-Sik Seok

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  G11C13/00

CPC分类号： G11C29/808 ,  G11C29/781

摘要： There is disclosed a redundant device for a semiconductor memory device comprising a plurality of normal cell arrays each having sense amplifier comprising an isolation gate for isolating or connecting the bit lines between adjacent ones of the normal cell arrays in response to isolation signal, a redundant cell array connected only with one of the adjacent redundant cell arrays, a control signal generating device for generating the isolation signal and a sensing signal to control the sense amplifiers respectively corresponding with the normal cell array connected with the redundant cell array and the normal cell array not connected with the redundant cell array, and device for generating a redundant control signal in response to a defect of an externally inputted address signal and a signal to select a word line of the redundant cell array.

摘要翻译： 公开了一种用于半导体存储器件的冗余设备，其包括多个正常单元阵列，每个正常单元阵列具有读出放大器，其包括用于响应于隔离信号隔离或连接相邻的正常单元阵列之间的位线的隔离栅极，冗余单元 阵列仅与相邻的冗余单元阵列中的一个连接，用于产生隔离信号的控制信号发生装置和分别对应于与冗余单元阵列连接的正常单元阵列和正常单元阵列的感测放大器的感测信号不是 与冗余单元阵列连接，以及用于响应于外部输入的地址信号的缺陷和用于选择冗余单元阵列的字线的信号而产生冗余控制信号的装置。

公开(公告)号：US5732029A

公开(公告)日：1998-03-24

申请号：US650398

申请日：1996-05-20

申请人： Sang-Kil Lee ,  Yong-Sik Seok

发明人： Sang-Kil Lee ,  Yong-Sik Seok

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/24 ,  G11C29/34 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C29/24 ,  G11C29/781

摘要： A test control circuit and method of testing a memory cell in a semiconductor memory device. The test control circuit includes a memory cell array having a plurality of normal memory cells to store data on a semiconductor substrate and a plurality of redundancy memory cells to substitute for defective normal memory cells. Row and column redundancy fuse boxes include fuse elements to be electrically fused to enable row and column redundancy decoders for selecting rows and columns of the redundancy memory cells. A redundancy cell test signal generator generates, in response to a test signal applied to an extra line in the address bus, a master clock for testing the redundancy memory cell under the same mode as a test mode of the normal memory cell. A test controller provides an enable signal for selecting the redundancy memory cells of a memory array in response to logic levels of the master clock and an address signal applied during the redundancy memory cell test.

摘要翻译： 一种测试半导体存储器件中的存储单元的测试控制电路和方法。 测试控制电路包括具有多个正常存储器单元的存储单元阵列，以在半导体衬底上存储数据，以及多个冗余存储单元来代替有缺陷的正常存储单元。 行和列冗余保险丝盒包括要电熔接的熔丝元件，以实现用于选择冗余存储器单元的行和列的行和列冗余解码器。 冗余单元测试信号发生器响应于施加到地址总线中的额外线路的测试信号而产生用于在与正常存储器单元的测试模式相同的模式下测试冗余存储单元的主时钟。 测试控制器提供用于响应于主时钟的逻辑电平和在冗余存储器单元测试期间施加的地址信号来选择存储器阵列的冗余存储单元的使能信号。

公开(公告)号：US5687128A

公开(公告)日：1997-11-11

申请号：US551005

申请日：1995-10-31

申请人： Jae-Hyeong Lee ,  Yong-Sik Seok

发明人： Jae-Hyeong Lee ,  Yong-Sik Seok

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  G11C13/00

CPC分类号： G11C5/145 ,  G11C11/4074

摘要： An active power supply voltage boosting circuit for a semiconductor memory device according to the present invention causes operation of the active cycle boosted voltage generating circuit to elevate the level of the boosted power supply voltage V.sub.PP when the detected level of the boosted power supply voltage V.sub.PP is lower than a target voltage level. Thus, the boosted power supply voltage V.sub.PP can be stably maintained to the target voltage level. When the boosted power supply voltage V.sub.PP becomes higher than the target voltage level, generation of the boosted power supply voltage V.sub.PP is stopped, and as a result, unwanted consumption of the electrical current and also the damage to the semiconductor memory device by high voltage can be prevented.

摘要翻译： 根据本发明的用于半导体存储器件的有源电源电压升压电路使检测到的升压电源电压VPP的电平为VPP时，主动周期升压电压产生电路的操作提升升压电源电压VPP的电平 低于目标电压电平。 因此，可以将升压电源电压VPP稳定地维持在目标电压电平。 当升压电源电压VPP变得高于目标电压电平时，升压的电源电压VPP的产生被停止，结果，电流的不必要的消耗以及高电压对半导体存储器件的损坏 被阻止

公开(公告)号：US5402378A

公开(公告)日：1995-03-28

申请号：US972522

申请日：1992-11-06

申请人： Kyung-Youl Min ,  Yong-Sik Seok

发明人： Kyung-Youl Min ,  Yong-Sik Seok

IPC分类号： G11C11/417 ,  G11C5/14 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C5/14 ,  G11C7/18 ,  G11C7/22

摘要： A semiconductor memory device using a low level supply voltage has separation gates for isolating adjacent bit lines. The device may be constructed with a circuit for receiving a high voltage supplied by a high voltage generator resident upon the chip so as to provide the separation gates with a voltage increased at least by the amount of the threshold voltage of the separation gates over the supply voltage.

摘要翻译： 使用低电平电源电压的半导体存储器件具有用于隔离相邻位线的分离栅极。 该器件可以构造有用于接收由驻留在芯片上的高电压发生器提供的高电压的电路，以便为分离门提供至少增加电源上的分离门的阈值电压的量的电压 电压。

公开(公告)号：US5293559A

公开(公告)日：1994-03-08

申请号：US770241

申请日：1991-10-03

申请人： Hyun-Soo Kim ,  Yong-Sik Seok

发明人： Hyun-Soo Kim ,  Yong-Sik Seok

IPC分类号： G11C5/14 ,  H01L27/10

CPC分类号： G11C5/14

摘要： A semiconductor memory device for minimizing the resistance attendant on reaching as far as each sense amplifier connected to a memory cell. A first plurality of power supply lines are alternatively disposed between column select lines which is formed over a plurality of lines of semiconductor memory device in a column direction. The first plurality of power supply lines the first plurality of ground lines are connected to a second plurality of power supply lines and a second plurality of ground lines which are disposed under the column select lines in a row direction, to thereby provide a netlike power supply structure. Consequently, the operating speed of a chip is improved by minimizing the resistance attendant on reaching as far as the sense amplifiers connected to each memory cell and the efficiency of the semiconductor memory device is greatly promoted by suppressing a coupling phenomenon caused between the column select lines.

摘要翻译： 一种半导体存储器件，用于使连接到存储器单元的每个读出放大器达到的电阻最小化。 交替地，第一组多个电源线设置在列列方向上形成在多条半导体存储器件行上的列选择线之间。 所述第一多个电源线与所述第二多个电源线连接，并且所述第二多个接地线设置在所述列选择线的行方向下方，从而提供网状电源 结构体。 因此，通过使连接到每个存储单元的感测放大器达到的电阻最小化来提高芯片的工作速度，并且通过抑制在列选择线之间引起的耦合现象来极大地促进半导体存储器件的效率 。