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11 条记录 (耗时 0.018 秒)

    Advanced process control framework using two-dimensional image analysis
    1.
    发明授权
    Advanced process control framework using two-dimensional image analysis 有权
    先进的过程控制框架采用二维图像分析

    公开(公告)号：US07875851B1

    公开(公告)日：2011-01-25

    申请号：US11381000

    申请日：2006-05-01

    申请人： Chris Haidinyak ,  Jason P. Cain ,  Bhanwar Singh

    发明人： Chris Haidinyak ,  Jason P. Cain ,  Bhanwar Singh

    IPC分类号： G01N21/88

    CPC分类号： H01L22/20 ,  G03F7/70525 ,  G03F7/70625 ,  G06T7/001 ,  G06T2207/10061 ,  G06T2207/30148 ,  H01L22/12

    摘要： The claimed subject matter provides a system and/or a method that facilitates utilizing a resolution enhancement for a circuit feature. A scanning electron microscope component (104, 204, 304, 404) can provide at least one two-dimensional image of the circuit feature. An image analysis engine (106, 206, 306, 406) can analyze the two-dimensional image. An advanced process control (APC) engine (108, 208, 308, 408) can generate at least one instruction for at least one of a feed forward control and a feedback control and a process component (102, 202, 302, 402) can utilize the at least one instruction to minimize an error.

    摘要翻译： 所要求保护的主题提供有助于利用电路特征的分辨率增强的系统和/或方法。 扫描电子显微镜组件（104,204,304,404）可以提供电路特征的至少一个二维图像。 图像分析引擎（106,206,306,406）可以分析二维图像。 高级过程控制（APC）引擎（108,208,308,408）可以为前馈控制和反馈控制中的至少一个生成至少一个指令，并且过程组件（102,202,302,402）可以 利用至少一个指令来最小化错误。

    Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results
    5.
    发明授权
    Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results 有权
    计量配方生成方法和系统，设计，模拟和计量结果的审查和分析

    公开(公告)号：US07207017B1

    公开(公告)日：2007-04-17

    申请号：US10865047

    申请日：2004-06-10

    申请人： Cyrus Tabery ,  Chris Haidinyak ,  Todd P. Lukanc ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

    发明人： Cyrus Tabery ,  Chris Haidinyak ,  Todd P. Lukanc ,  Luigi Capodieci ,  Carl P. Babcock ,  Hung-eil Kim ,  Christopher A. Spence

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

    摘要翻译： 生成计量配方的方法包括识别设备布局内的感兴趣区域。 可以提供对应于所识别的感兴趣区域的坐标列表并用于创建剪切布局，其可以由剪切布局数据文件表示。 裁剪的布局数据文件和相应的坐标列表可以被提供并转换成用于在测试处理的晶片和/或掩模版时引导一个或多个计量仪器的计量配方。 根据测量要求收到的实验测量结果可以与相应的设计数据和仿真数据相关联，并存储在可数据库系统中。

    Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
    7.
    发明授权
    Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin 有权
    通过考虑布局交互以及额外的可制造性边际来优化集成电路布局

    公开(公告)号：US07313769B1

    公开(公告)日：2007-12-25

    申请号：US10790381

    申请日：2004-03-01

    申请人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

    发明人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

    摘要翻译： 产生对应于集成电路（IC）设备设计的布局表示的方法可以包括根据预定的一组设计规则生成初始布局表示，并且模拟初始布局表示中的结构如何在晶片上进行图案化。 基于模拟，可以识别布局表示的部分，其包括展示不良可制造性的结构和/或其中存在额外的可制造裕度的布局表示的部分。 可以修改布局表示的部分，包括显示不良可制造性的结构和/或存在额外的可制造性裕度的部分，以优化布局表示。

    Method and system for determining optimum optical proximity corrections within a photolithography system
    8.
    发明授权
    Method and system for determining optimum optical proximity corrections within a photolithography system 有权
    用于确定光刻系统内的最佳光学邻近校正的方法和系统

    公开(公告)号：US06982136B1

    公开(公告)日：2006-01-03

    申请号：US10966854

    申请日：2004-10-15

    申请人： Chris Haidinyak

    发明人： Chris Haidinyak

    IPC分类号： G03F9/00 ,  G06F17/50

    CPC分类号： G06T7/001 ,  G03F1/36 ,  G03F1/44 ,  G03F1/68 ,  G06T2207/30148

    摘要： For determining optimum optical proximity corrections (OPCs) for a mask pattern, mask areas are formed on a reticle with each mask area having the mask pattern of polygons that are modified with respective OPCs perturbations. A respective patterned area is fabricated on a semiconductor wafer from each mask area of the reticle. A respective microscopy image of each respective patterned area is generated to determine a respective error function for each mask area by comparing a desired image of the mask pattern and the respective microscopy image. The optimum OPCs are determined as the respective OPCs perturbations corresponding to one of the mask areas having the respective error function that is a minimum of the mask areas.

    摘要翻译： 为了确定用于掩模图案的最佳光学邻近校正（OPC），掩模区域形成在掩模版上，每个掩模区域具有用相应的OPCs扰动修改的多边形的掩模图案。 在半导体晶片上从掩模版的每个掩模区域制造相应的图案化区域。 通过比较掩模图案的期望图像和相应的显微镜图像，产生每个相应图案化区域的相应显微镜图像以确定每个掩模区域的相应误差函数。 将最佳OPC确定为对应于具有作为掩模区域的最小值的相应误差函数的掩模区域之一的相应OPCs扰动。