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    Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
    4.
    发明授权
    Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin 有权
    通过考虑布局交互以及额外的可制造性边际来优化集成电路布局

    公开(公告)号：US07313769B1

    公开(公告)日：2007-12-25

    申请号：US10790381

    申请日：2004-03-01

    申请人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

    发明人： Todd P. Lukanc ,  Cyrus E. Tabery ,  Luigi Capodieci ,  Carl Babcock ,  Hung-Eil Kim ,  Christopher A. Spence ,  Chris Haidinyak

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

    摘要翻译： 产生对应于集成电路（IC）设备设计的布局表示的方法可以包括根据预定的一组设计规则生成初始布局表示，并且模拟初始布局表示中的结构如何在晶片上进行图案化。 基于模拟，可以识别布局表示的部分，其包括展示不良可制造性的结构和/或其中存在额外的可制造裕度的布局表示的部分。 可以修改布局表示的部分，包括显示不良可制造性的结构和/或存在额外的可制造性裕度的部分，以优化布局表示。

    System and method for fabricating contact holes
    6.
    发明授权
    System and method for fabricating contact holes 有权
    制造接触孔的系统和方法

    公开(公告)号：US07384725B2

    公开(公告)日：2008-06-10

    申请号：US10817193

    申请日：2004-04-02

    申请人： Anna M. Minvielle ,  Cyrus E. Tabery ,  Hung-eil Kim ,  Jongwook Kye

    发明人： Anna M. Minvielle ,  Cyrus E. Tabery ,  Hung-eil Kim ,  Jongwook Kye

    IPC分类号： G03F7/20 ,  G03F1/00

    CPC分类号： G03F7/70425 ,  G03F7/70091 ,  G03F7/701 ,  G03F7/70125 ,  G03F7/70158

    摘要： A method of forming a plurality of contact holes of varying pitch and density in a contact layer of an integrated circuit device is provided. The plurality of contact holes can include a plurality of regularly spaced contact holes having a first pitch along a first direction and a plurality of semi-isolated contact holes having a second pitch along a second direction. A double-dipole illumination source can transmit light energy through a mask having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source can include a first dipole aperture, which is oriented and optimized for patterning the regularly spaced contact holes, and a second dipole aperture, which is oriented substantially orthogonal to the first dipole aperture and optimized for patterning the plurality of semi-isolated contact holes. The contact layer can be etched using the patterned photoresist layer.

    摘要翻译： 提供了一种在集成电路器件的接触层中形成多个具有不同间距和密度的接触孔的方法。 多个接触孔可以包括沿着第一方向具有第一间距的多个规则间隔的接触孔和沿第二方向具有第二间距的多个半隔离接触孔。 双偶极照明源可以通过具有对应于期望的接触孔图案的图案的掩模传输光能。 双偶极照明源可以包括第一偶极孔，其被定向和优化以用于图案化规则间隔的接触孔，以及第二偶极孔，其基本上垂直于第一偶极孔定向并且被优化用于图案化多个半 隔离接触孔。 可以使用图案化的光致抗蚀剂层来蚀刻接触层。

    METHOD AND APPARATUS FOR MONITORING OPTICAL PROXIMITY CORRECTION PERFORMANCE
    7.
    发明申请
    METHOD AND APPARATUS FOR MONITORING OPTICAL PROXIMITY CORRECTION PERFORMANCE 审中-公开
    用于监测光学近似校正性能的方法和装置

    公开(公告)号：US20090144692A1

    公开(公告)日：2009-06-04

    申请号：US11948151

    申请日：2007-11-30

    申请人： JASON P. CAIN ,  Kevin R. Lensing ,  Bhanwar Singh ,  Luigi Capodieci ,  Cyrus E. Tabery

    发明人： JASON P. CAIN ,  Kevin R. Lensing ,  Bhanwar Singh ,  Luigi Capodieci ,  Cyrus E. Tabery

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36 ,  G03F1/68

    摘要： A method includes specifying a plurality of optical proximity correction metrology sites on a wafer. Metrology data is collected from at least a subset of the metrology sites. Data values are predicted for the subset of the metrology sites using an optical proximity correction design model. The collected metrology data is compared to the predicted data values to generate an optical proximity correction metric. A problem condition associated with the optical proximity correction design model is identified based on the optical proximity correction metric.

    摘要翻译： 一种方法包括在晶片上指定多个光学邻近校正度量位置。 计量学数据是从至少一个计量站点子集收集的。 使用光学邻近校正设计模型为量测站点的子集预测数据值。 将收集的测量数据与预测的数据值进行比较以产生光学邻近度校正度量。 基于光学邻近度校正度量来识别与光学接近校正设计模型相关联的问题状况。

    METHOD AND APPARATUS FOR MONITORING MARGINAL LAYOUT DESIGN RULES
    8.
    发明申请
    METHOD AND APPARATUS FOR MONITORING MARGINAL LAYOUT DESIGN RULES 审中-公开
    用于监测标准布局设计规则的方法和装置

    公开(公告)号：US20090144686A1

    公开(公告)日：2009-06-04

    申请号：US11948218

    申请日：2007-11-30

    申请人： KEVIN R. LENSING ,  Jason P. Cain ,  Bhanwar Singh ,  Luigi Capodieci ,  Cyrus E. Tabery

    发明人： KEVIN R. LENSING ,  Jason P. Cain ,  Bhanwar Singh ,  Luigi Capodieci ,  Cyrus E. Tabery

    IPC分类号： G06F19/00

    CPC分类号： G06F17/5081

    摘要： A method includes generating a layout for an integrated circuit device in accordance with a plurality of layout design rules. A plurality of metrology sites on the layout associated with at least one subset of the layout design rules is identified. A metrology tag associated with each of the metrology sites is generated. At least one metrology recipe for determining a characteristic of the integrated circuit device is generated based on the metrology tags. Metrology data is collected using the at least one metrology recipe. A selected layout design rule in the at least one subset is modified based on the metrology data.

    摘要翻译： 一种方法包括根据多个布局设计规则生成用于集成电路设备的布局。 识别与布局设计规则的至少一个子集相关联的布局上的多个计量站点。 生成与每个测量点相关联的度量标签。 基于计量标签生成至少一个用于确定集成电路装置的特性的计量配方。 使用至少一个计量学方法收集计量学数据。 基于测量数据修改至少一个子集中的选定的布局设计规则。

    Double and triple gate MOSFET devices and methods for making same
    9.
    发明授权
    Double and triple gate MOSFET devices and methods for making same 有权
    双栅极和三栅极MOSFET器件及其制造方法

    公开(公告)号：US08222680B2

    公开(公告)日：2012-07-17

    申请号：US10274961

    申请日：2002-10-22

    申请人： Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

    发明人： Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

    IPC分类号： H01L29/72

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66818

    摘要： A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

    摘要翻译： 双栅极金属氧化物半导体场效应晶体管（MOSFET）包括鳍状物，第一栅极和第二栅极。 第一个门形成在鳍的顶部。 第二个门围绕翅片和第一个门。 在另一实施方案中，三栅极MOSFET包括鳍片，第一栅极，第二栅极和第三栅极。 第一个门形成在鳍的顶部。 第二个门形成在翅片附近。 第三栅极形成在翅片附近并与第二栅极相对。

    Method of using carbon spacers for critical dimension (CD) reduction
    10.
    发明授权
    Method of using carbon spacers for critical dimension (CD) reduction 失效
    使用碳间隔物进行临界尺寸（CD）还原的方法

    公开(公告)号：US07169711B1

    公开(公告)日：2007-01-30

    申请号：US10170984

    申请日：2002-06-13

    申请人： Christopher F. Lyons ,  Philip A. Fisher ,  Richard J. Huang ,  Cyrus E. Tabery

    发明人： Christopher F. Lyons ,  Philip A. Fisher ,  Richard J. Huang ,  Cyrus E. Tabery

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3086 ,  H01L21/0337

    摘要： A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.

    摘要翻译： 使用碳间隔物进行临界尺寸减小的方法可以包括在基底上提供图案化的光致抗蚀剂层，其中图案化的光致抗蚀剂层具有第一宽度的孔，在光致抗蚀剂层上沉积碳膜并蚀刻沉积的碳膜以形成间隔物 在图案化光致抗蚀剂层的孔的侧壁上，使用所形成的间隔物和图案化的光致抗蚀剂层作为图案蚀刻衬底，以形成具有第二宽度的沟槽，并使用氧化蚀刻去除图案化的光致抗蚀剂层和形成的间隔物。