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公开(公告)号：US07692447B2
公开(公告)日：2010-04-06
申请号：US12115933
申请日：2008-05-06
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K17/164 , H04L25/0278 , H04L25/028
摘要： A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.
摘要翻译： 提供了驱动器电路，其包括至少两个相等的主单元（MU），每个主单元包括耦合到数据输出（dout）的至少两个子单元（SU）。 每个子单元（SU）适于表示相应的预定阻抗。 每个主单元（MU）适于当处于数据模式时，根据要发送的数据信号，各个主单元（MU）的每个子单元（SU）可切换到第一或第二参考电位。 每个主单元（MU）还适用于当处于终止模式时，相应主单元（MU）的子单元（SU）被切换到第一或第二参考电位，使得各个主单元（MU）的输出 单位（MU）相对于第一或第二参考电位的数据输出（dout）的驱动是中性的。
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公开(公告)号：US20080284466A1
公开(公告)日：2008-11-20
申请号：US12115933
申请日：2008-05-06
IPC分类号： H03K19/003
CPC分类号： H03K19/0005 , H03K17/164 , H04L25/0278 , H04L25/028
摘要： A driver circuit is provided comprising at least two equal main units (MU) each comprising at least two sub units (SU) coupled to a data output (dout). Each sub unit (SU) is adapted to represent a respective predetermined impedance. Each main unit (MU) is adapted to that, when in a data mode, each sub unit (SU) of the respective main unit (MU) is switchable to either a first or second reference potential depending on a data signal to transmit. Each main unit (MU) is further adapted to that, when in a termination mode, the sub units (SU) of the respective main unit (MU) are switched to either the first or second reference potential such that an output of the respective main unit (MU) is neutral with respect to the driving of the data output (dout) to the first or second reference potential.
摘要翻译： 提供了驱动器电路，其包括至少两个相等的主单元（MU），每个主单元包括耦合到数据输出（dout）的至少两个子单元（SU）。 每个子单元（SU）适于表示相应的预定阻抗。 每个主单元（MU）适于当处于数据模式时，根据要发送的数据信号，各个主单元（MU）的每个子单元（SU）可切换到第一或第二参考电位。 每个主单元（MU）还适用于当处于终止模式时，相应主单元（MU）的子单元（SU）被切换到第一或第二参考电位，使得各个主单元（MU）的输出 单位（MU）相对于第一或第二参考电位的数据输出（dout）的驱动是中性的。
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公开(公告)号：US08170157B2
公开(公告)日：2012-05-01
申请号：US11961545
申请日：2007-12-20
IPC分类号： H04L27/08
CPC分类号： H04L7/0008 , H03L7/07 , H03L7/08 , H03L7/0805 , H04L7/0037
摘要： The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by the delayed jitter signal.
摘要翻译： 所述通信系统具有发射机和接收机，其中所述发射机和所述接收机通过时钟信道和数据信道耦合，其中所述时钟信道比所述数据信道短，并且其中所述接收机包括用于提取抖动信号的延迟电路 从时钟信道信号延迟提取的抖动信号，并通过延迟的抖动信号产生接收机的接收机时钟信号。
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公开(公告)号：US20090002082A1
公开(公告)日：2009-01-01
申请号：US11962681
申请日：2007-12-21
IPC分类号： H03L7/08
CPC分类号： H03L7/0995 , H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/06 , H04L7/033 , H04L7/0337
摘要： A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.
摘要翻译： 用于产生多相的信号发生器包括具有至少一个第一可调节延迟级的环形振荡器和串行布置的至少一个第二延迟级，其中第一延迟级的输出被提供用于传送至少一个第一输出相位和 提供第二延迟级的输出用于传递至少一个第二输出相位和用于调整第一可调延迟级的延迟的调整电路，其中调整电路用于调整第一输出相位与第一输出相位之间的相位关系 通过设置第一延迟级的第一传播延迟来实现第二输出相位。
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公开(公告)号：US07679459B2
公开(公告)日：2010-03-16
申请号：US11962681
申请日：2007-12-21
IPC分类号： H03B27/00
CPC分类号： H03L7/0995 , H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/06 , H04L7/033 , H04L7/0337
摘要： A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.
摘要翻译： 用于产生多相的信号发生器包括具有至少一个第一可调节延迟级的环形振荡器和串行布置的至少一个第二延迟级，其中第一延迟级的输出被提供用于传送至少一个第一输出相位和 提供第二延迟级的输出用于传递至少一个第二输出相位和用于调整第一可调延迟级的延迟的调整电路，其中调整电路用于调整第一输出相位与第一输出相位之间的相位关系 通过设置第一延迟级的第一传播延迟来实现第二输出相位。
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6.发明授权Method and system for low-power integrating decision feedback equalizer with fast switched-capacitor feed forward path 失效具有快速开关电容器前馈路径的低功率积分判决反馈均衡器的方法和系统公开(公告)号：US07539243B1
公开(公告)日：2009-05-26
申请号：US12060140
申请日：2008-03-31
CPC分类号： H04L25/03057 , H04L2025/0349
摘要： A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.
摘要翻译： 提供了一种用于数字传输系统的判决反馈均衡的方法和系统。 使用具有快速开关电容路径的低功率积分判决反馈均衡，用于抑制由于过去的数据符号引起的符号间干扰（ISI）。 判定反馈均衡涉及在电流积分缓冲器的输出处采用快速电容耦合前馈路径的低功率执行电流积分判决反馈均衡，并通过耦合的开关电容器通过电荷再分配来感应电压变化，并且执行电压 数字到模拟对话，以确定反馈系数作为耦合电压。 然后，开关被复位到缓冲器中的预充电耦合电压，以消除由信号历史引起的剩余ISI，从而在积分期间实现电流积分缓冲与开关电容器反馈，并且电容开关由先前的符号触发。
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公开(公告)号：US20080175344A1
公开(公告)日：2008-07-24
申请号：US11961545
申请日：2007-12-20
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H03L7/07 , H03L7/08 , H03L7/0805 , H04L7/0037
摘要： The communication system having a transmitter and a receiver, wherein the transmitter and the receiver are coupled by a clock channel and a data channel, wherein the clock channel is shorter than the data channel and wherein the receiver comprises a delay circuit for extracting a jitter signal from a clock channel signal, delaying the extracted jitter signal, and generating a receiver clock signal for the receiver by means of the delayed jitter signal.
摘要翻译： 所述通信系统具有发射机和接收机，其中所述发射机和所述接收机通过时钟信道和数据信道耦合，其中所述时钟信道比所述数据信道短，并且其中所述接收机包括用于提取抖动信号的延迟电路 从时钟信道信号延迟提取的抖动信号，并通过延迟的抖动信号产生接收机的接收机时钟信号。
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公开(公告)号：US08917762B2
公开(公告)日：2014-12-23
申请号：US13486644
申请日：2012-06-01
CPC分类号： H04L25/03146 , H04L2025/03484
摘要： A decision feedback equalizer (DFE) slice for a receiver includes a plurality of non-speculative DFE taps; and 3 speculative DFE taps, wherein the 3 speculative DFE taps comprise first and second multiplexer stages, each of the first and second multiplexer stages including 4 comparator latches, each of the 4 comparator latches having a programmable offset; and a multiplexer that receives 4 comparator latch outputs from the 4 comparator latches and outputs a multiplexer stage output, wherein the multiplexer is controlled by previous symbol decisions dn-2 and dn-3; and wherein the 3 speculative taps further comprise a 2:1 decision multiplexer stage that receives the multiplexer stage outputs of the first and second multiplexer stages and is controlled by a previous symbol decision dn-1 to output a slice output signal dn.
摘要翻译： 用于接收机的判决反馈均衡器（DFE）片包括多个非投机DFE抽头; 和3个推测性DFE抽头，其中3个推测性DFE抽头包括第一和第二多路复用器级，第一和第二多路复用器级中的每一个包括4个比较器锁存器，4个比较器锁存器中的每一个具有可编程偏移量; 以及多路复用器，其从4个比较器锁存器接收4个比较器锁存器输出并输出多路复用器级输出，其中多路复用器由先前的符号决定dn-2和dn-3控制; 并且其中所述3个推测抽头还包括2：1判决复用器级，其接收所述第一和第二多路复用器级的多路复用器级输出，并由先前的符号判定dn-1控制以输出片输出信号dn。
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公开(公告)号：US20130200934A1
公开(公告)日：2013-08-08
申请号：US13367777
申请日：2012-02-07
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.
摘要翻译： 占空比调整电路包括时钟信号输入节点; 时钟信号输出节点; 耦合到所述时钟信号输入节点的控制电压产生电路; 以及第一反相器，被配置为接收包括在时钟信号输入节点处接收的输入时钟信号和从控制电压产生电路接收的控制电压之和的反相器输入信号，并且在时钟信号输出端输出输出时钟信号 节点，其中所述控制电压的变化被配置为改变所述输出时钟信号的占空比。
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公开(公告)号：US20090060091A1
公开(公告)日：2009-03-05
申请号：US11848599
申请日：2007-08-31
IPC分类号： H04L27/00
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/091 , H03L7/10 , H04L7/0008
摘要： A high-speed receiver includes multiple receiver components. Each receiver component includes sampling latches for receiving data, phase rotators for controlling timing of sampling of data by the sampling latches, and a clock-tracking logic stage for providing clock and data recovery. The clock-tracking logic stage is divided into a high-speed early/late (E/L) logic and aggregation counter section and a low-speed logic section, separated by a synchronization logic block. The receiver also includes a delay locked loop (DLL) for receiving an input clock signal corresponding to a data rate of the received data, providing coarse delay adjustment of the clock signal and outputting multiple clock phase vectors corresponding to the adjusted clock signal to the phase rotators on each receiver component. The phase rotators control sampling of the data based on the clock phase vectors received from the DLL. A single regulated power supply regulator regulates power supplied to the DLL and the phase rotators.
摘要翻译： 高速接收机包括多个接收机组件。 每个接收器组件包括用于接收数据的采样锁存器，用于控制由采样锁存器采样数据的定时的相位旋转器以及用于提供时钟和数据恢复的时钟跟踪逻辑级。 时钟跟踪逻辑级分为高速早/晚（E / L）逻辑和聚合计数器部分以及由同步逻辑块分隔的低速逻辑部分。 接收机还包括用于接收对应于接收数据的数据速率的输入时钟信号的延迟锁定环路（DLL），提供时钟信号的粗略的延迟调整，并将对应于经调整的时钟信号的多个时钟相位矢量输出到相位 每个接收器组件上的旋转器。 相位旋转器基于从DLL接收的时钟相位矢量来控制数据的采样。 单个稳压电源调节器调节提供给DLL和相位旋转器的电源。
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