公开(公告)号：US20050110800A1

公开(公告)日：2005-05-26

申请号：US10954526

申请日：2004-09-29

申请人： Christopher Putnam ,  Mark Anderson

发明人： Christopher Putnam ,  Mark Anderson

IPC分类号： G06K9/54

CPC分类号： G06F17/30241

摘要： A CAD/GIS system that dynamically updates planar topologies through incremental updating techniques. Rather than batch processing all of the changes to every geometrical feature in a given site map, the changes are made in incremental fashion and only enclosures or faces/parcels that are affected by changes are updated.

摘要翻译： CAD / GIS系统，通过增量更新技术动态更新平面拓扑。 在批处理给定站点地图中对每个几何特征的所有更改进行批处理，而不是以增量方式进行更改，而只会更改受更改影响的外壳或面/面包。

公开(公告)号：US20050114107A1

公开(公告)日：2005-05-26

申请号：US10954542

申请日：2004-09-29

申请人： Christopher Putnam ,  Mark Anderson

发明人： Christopher Putnam ,  Mark Anderson

IPC分类号： G06F17/50

CPC分类号： G06T17/05

摘要： A CAD/GIS system that automatically discovers hierarchical relationships between root faces/parcels, smaller faces/parcels, and other defined areas of land. As the definitions are entered into the system, hierarchical relationships are created by the system to ease data management functions.

摘要翻译： CAD / GIS系统，自动发现根面/包裹，较小的面孔/包裹和其他定义的土地区域之间的分层关系。 当定义被输入到系统中时，系统创建层次关系以简化数据管理功能。

公开(公告)号：US20050114017A1

公开(公告)日：2005-05-26

申请号：US10954529

申请日：2004-09-29

申请人： Christopher Putnam ,  Mark Anderson

发明人： Christopher Putnam ,  Mark Anderson

IPC分类号： G01C21/30

CPC分类号： G06T17/05 ,  G01C21/32 ,  G06F17/50 ,  G06F2217/38 ,  G09B29/007

摘要： A CAD/GIS system that automatically generates faces within land site maps, by sliding or rotating line segments between boundaries given start points and other attributes. As the attributes are entered into the system, faces are automatically generated based on those attributes, which eases creation of lots within subdivisions.

摘要翻译： CAD / GIS系统，通过滑动或旋转给定起始点和其他属性的边界之间的线段，自动生成陆地地图中的面孔。 当属性输入到系统中时，将根据这些属性自动生成面，从而简化了分区内批次的创建。

公开(公告)号：US20060157799A1

公开(公告)日：2006-07-20

申请号：US10905682

申请日：2005-01-17

申请人： Kiran Chatty ,  Robert Gauthier ,  Terence Hook ,  Christopher Putnam ,  Mujahid Muhammad

发明人： Kiran Chatty ,  Robert Gauthier ,  Terence Hook ,  Christopher Putnam ,  Mujahid Muhammad

IPC分类号： H01L29/76

CPC分类号： H01L29/78 ,  H01L27/027

摘要： A field effect transistor with associated parasitic lateral npn bipolar junction transistor includes a source region in a substrate, a channel region in the substrate laterally adjacent to the source region, a drain region in the substrate laterally adjacent to the channel region, and a gate above the channel region of the substrate. In addition, a reduced trigger voltage region of the substrate is positioned below the drain region. The reduced trigger voltage region has a threshold voltage of about zero and comprises an undoped region of the pure wafer substrate. Thus, the reduced trigger voltage region is free of implanted N-type and P-type doping.

摘要翻译： 具有相关联的寄生横向npn双极结型晶体管的场效应晶体管包括衬底中的源极区域，与源极区域横向相邻的衬底中的沟道区域，衬底中的与沟道区域横向相邻的漏极区域，以及位于 衬底的沟道区域。 此外，衬底的降低的触发电压区域位于漏极区域的下方。 降低的触发电压区域具有约零的阈值电压，并且包括纯晶片衬底的未掺杂区域。 因此，降低的触发电压区域没有注入的N型和P型掺杂。

公开(公告)号：US20050068315A1

公开(公告)日：2005-03-31

申请号：US10953245

申请日：2004-09-29

申请人： John Lewis ,  Robert Todd ,  Edward Connor ,  Christopher Putnam

发明人： John Lewis ,  Robert Todd ,  Edward Connor ,  Christopher Putnam

IPC分类号： G06F17/00 ,  G06T17/40

CPC分类号： G06T19/20 ,  G06T2200/24 ,  G06T2219/2021 ,  Y10S715/964

摘要： A method, apparatus, and article of manufacture provide the ability to manipulate a drawing surface in a CAD/GIS computer application. A drawing surface is displayed in a CAD/GIS application followed by the performance of a surface edit operation on the drawing surface. The surface edit operation is stored/saved as an atomic property in a list of surface edit operations. The list of surface edit operations is displayed in a graphical user interface (GUI). Each surface edit operation may be independently toggled on/off in the GUI and such toggling is reflected in the CAD/GIS application by displaying an effect of executing the surface edit operation if toggled on and displaying the drawing surface without execution of the surface edit operation if toggled off.

摘要翻译： 一种方法，装置和制品提供了在CAD / GIS计算机应用中操纵绘图表面的能力。 绘图表面显示在CAD / GIS应用程序中，然后在图面上执行表面编辑操作。 表面编辑操作被存储/保存为表面编辑操作列表中的原子属性。 表面编辑操作的列表显示在图形用户界面（GUI）中。 每个表面编辑操作可以在GUI中独立地切换/切换，并且如果切换并显示绘图表面而不执行表面编辑操作，则通过显示执行表面编辑操作的效果来反映在CAD / GIS应用中 如果切换。

公开(公告)号：US20080050880A1

公开(公告)日：2008-02-28

申请号：US11931634

申请日：2007-10-31

申请人： Michel Abou-Khalil ,  Robert Gauthier ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher Putnam

发明人： Michel Abou-Khalil ,  Robert Gauthier ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher Putnam

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/458 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method in which a low-resistance connection between the MOS channel and silicided source/drain regions is provided that has an independence from the extension ion implant process as well as device overlap capacitance. The method of the present invention broadly includes selectively removing outer spacers of an MOS structure and then selectively plating a metallic or intermetallic material on exposed portions of a semiconductor substrate that were previously protected by the outer spacers. The present invention also provides a semiconductor structure that is formed utilizing the method. The semiconductor structure includes a low-resistance connection between the silicided source/drain regions and the channel regions which includes a selectively plated metallic or intermetallic material.

摘要翻译： 本发明提供了一种方法，其中提供了与扩展离子注入工艺无关的MOS沟道和硅化源极/漏极区之间的低电阻连接以及器件重叠电容。 本发明的方法广泛地包括选择性地去除MOS结构的外部间隔物，然后在先前由外部间隔物保护的半导体衬底的暴露部分上选择性地镀覆金属或金属间化合物。 本发明还提供了利用该方法形成的半导体结构。 半导体结构包括硅化源/漏区和沟道区之间的低电阻连接，其包括选择性镀金属或金属间化合物。

公开(公告)号：US20070262345A1

公开(公告)日：2007-11-15

申请号：US11781370

申请日：2007-07-23

申请人： Robert Gauthier ,  Junjun Li ,  Souvick Mitra ,  Mahmoud Mousa ,  Christopher Putnam

发明人： Robert Gauthier ,  Junjun Li ,  Souvick Mitra ,  Mahmoud Mousa ,  Christopher Putnam

IPC分类号： H01L21/02 ,  H01L29/66

CPC分类号： H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

摘要： A silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

摘要翻译： 硅控制整流器，制造硅控制整流器的方法和使用硅控制整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US20070170512A1

公开(公告)日：2007-07-26

申请号：US11275638

申请日：2006-01-20

申请人： Robert Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud Mousa ,  Christopher Putnam

发明人： Robert Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud Mousa ,  Christopher Putnam

IPC分类号： H01L23/62

CPC分类号： H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

摘要： Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

摘要翻译： 公开了一种硅控制整流器，制造硅控制整流器的方法和使用硅控整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US20060043571A1

公开(公告)日：2006-03-02

申请号：US10711167

申请日：2004-08-30

申请人： Mahmoud Mousa ,  Christopher Putnam

发明人： Mahmoud Mousa ,  Christopher Putnam

IPC分类号： H01L23/12

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  Y10S257/903

摘要： An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with a active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.

摘要翻译： 提供了一种用于多层硅绝缘体（SOI）器件的设备和方法。 在多层SOI器件中，器件的至少一个有源区域的晶体取向与至少另一器件的有源区域不同。 在多层SOI器件具有包括具有[100]晶体取向的硅有源区的PMOS器件的第一层的情况下，第二层可以是具有晶体取向为[110]的具有硅层的有源区的NMOS器件 ]。 第二层结合到第一层。 该方法和装置可以扩展到两层以上，从而形成在每层具有不同晶体取向的多层SOI器件。 多层SOI器件可形成表面积减小的电路。

公开(公告)号：US20050224882A1

公开(公告)日：2005-10-13

申请号：US10709041

申请日：2004-04-08

申请人： Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

发明人： Kiran Chatty ,  Robert Gauthier ,  Mujahid Muhammad ,  Christopher Putnam

IPC分类号： H01L23/62 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L29/0653 ,  H01L29/1083 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD NMOSFET, and a method for lowering a ESD NMOSFET trigger voltage. An ESD NMOSFET is configured in triple well CMOS architecture where the first well is separated from second and third wells by respective shallow well isolation regions. The first well is also separated from the substrate along the bottom by a conductive band region. A substrate contact is located outside of the first, second and third wells, and provides a current path during an ESD event from the first well. Source and drain regions are formed in the first well, to form an FET with the drain being connected to an I/O pad which is subject to an ESD event. A resistive path extends through an opening in the conductive band region to a substrate contact, providing an increased I/O pad to substrate resistance which decreases the trigger voltage for the ESD NMOSFET.

摘要翻译： ESD NMOSFET，以及降低ESD NMOSFET触发电压的方法。 ESD NMOSFET配置在三阱CMOS结构中，其中第一阱通过相应的浅阱隔离区与第二阱和第三阱分离。 第一阱也通过导电带区沿着底部与衬底分离。 衬底触点位于第一，第二和第三阱的外部，并且在来自第一阱的ESD事件期间提供电流路径。 源极和漏极区域形成在第一阱中，以形成FET，其漏极连接到经受ESD事件的I / O焊盘。 电阻路径延伸穿过导电带区域中的开口到衬底接触，从而为衬底电阻提供增加的I / O焊盘，从而降低ESD NMOSFET的触发电压。