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    Method of fabricating metal oxide semiconductor transistor
    1.
    发明授权
    Method of fabricating metal oxide semiconductor transistor 有权
    制造金属氧化物半导体晶体管的方法

    公开(公告)号：US08076194B2

    公开(公告)日：2011-12-13

    申请号：US12781826

    申请日：2010-05-18

    申请人： Chu-Yin Tseng ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Shyh-Fann Ting ,  Po-Lun Cheng ,  Hsuan-Hsu Chen

    发明人： Chu-Yin Tseng ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Shyh-Fann Ting ,  Po-Lun Cheng ,  Hsuan-Hsu Chen

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848

    摘要： A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.

    摘要翻译： 公开了制造MOS晶体管的方法。 该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成至少栅极; 在所述半导体衬底上形成保护层，所述保护层覆盖所述栅极表面; 在所述半导体衬底内至少形成与所述栅极相邻的凹部; 在所述凹部中形成外延层，其中所述外延层的顶表面在所述半导体衬底的表面之上; 以及在所述栅极的侧壁和所述外延层的一部分上形成间隔物，其中所述外延层和所述间隔物的接触表面在所述半导体衬底的表面之上。

    Method of fabricating metal oxide semiconductor transistor
    3.
    发明申请
    Method of fabricating metal oxide semiconductor transistor 有权
    制造金属氧化物半导体晶体管的方法

    公开(公告)号：US20100227445A1

    公开(公告)日：2010-09-09

    申请号：US12781826

    申请日：2010-05-18

    申请人： Chu-Yin Tseng ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Shyh-Fann Ting ,  Po-Lun Cheng ,  Hsuan-Hsu Chen

    发明人： Chu-Yin Tseng ,  Shih-Chieh Hsu ,  Chih-Chiang Wu ,  Shyh-Fann Ting ,  Po-Lun Cheng ,  Hsuan-Hsu Chen

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848

    摘要： A method of fabricating a MOS transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming at least a gate on the semiconductor substrate; forming a protective layer on the semiconductor substrate, and the protective layer covering the surface of the gate; forming at least a recess within the semiconductor substrate adjacent to the gate; forming an epitaxial layer in the recess, wherein the top surface of the epitaxial layer is above the surface of the semiconductor substrate; and forming a spacer on the sidewall of the gate and on a portion of the epitaxial layer, wherein a contact surface of the epitaxial layer and the spacer is above the surface of the semiconductor substrate.

    摘要翻译： 公开了制造MOS晶体管的方法。 该方法包括以下步骤：提供半导体衬底; 在所述半导体衬底上形成至少栅极; 在所述半导体衬底上形成保护层，所述保护层覆盖所述栅极表面; 在所述半导体衬底内至少形成与所述栅极相邻的凹部; 在所述凹部中形成外延层，其中所述外延层的顶表面在所述半导体衬底的表面之上; 以及在所述栅极的侧壁和所述外延层的一部分上形成间隔物，其中所述外延层和所述间隔物的接触表面在所述半导体衬底的表面之上。

    MOS transistor and fabrication thereof
    5.
    发明授权
    MOS transistor and fabrication thereof 有权
    MOS晶体管及其制造

    公开(公告)号：US07592231B2

    公开(公告)日：2009-09-22

    申请号：US11461639

    申请日：2006-08-01

    申请人： Po-Lun Cheng ,  Che-Hung Liu

    发明人： Po-Lun Cheng ,  Che-Hung Liu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66628 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

    摘要： A method of fabricating a MOS transistor is described. A substrate is provided, and then a composite layer for forming a gate structure and a carbon-containing mask material layer are formed thereon in turn, wherein the carbon-containing mask material layer is formed with a carbon-containing precursor gas and a reaction gas. The carbon-containing mask material layer and the composite layer are patterned into a carbon-containing hard mask layer and a gate structure, respectively. A spacer is formed on the sidewalls of the gate structure and the carbon-containing hard mask layer. A passivation layer is formed over the substrate, and then a portion of the passivation layer is removed to expose a portion of the substrate. A doped epitaxial layer is formed on the exposed portion of the substrate.

    摘要翻译： 描述制造MOS晶体管的方法。 提供基板，然后依次形成用于形成栅极结构和含碳掩模材料层的复合层，其中含碳掩模材料层由含碳前体气体和反应气体形成 。 将含碳掩模材料层和复合层分别图案化为含碳硬掩模层和栅极结构。 在栅极结构和含碳硬掩模层的侧壁上形成间隔物。 在衬底上形成钝化层，然后去除钝化层的一部分以露出衬底的一部分。 在衬底的暴露部分上形成掺杂的外延层。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20080191206A1

    公开(公告)日：2008-08-14

    申请号：US11673161

    申请日：2007-02-09

    申请人： Po-Lun Cheng

    发明人： Po-Lun Cheng

    IPC分类号： H01L29/04 ,  H01L21/336

    CPC分类号： H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/66636

    摘要： A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a first poly-SiGe layer being boron-doped and a second poly-SiGe layer being boron-doped. The substrate has two openings and the gate structure is disposed on the substrate between the openings. The spacer is disposed on the sidewalls of the gate structure and above a portion of the openings. The first poly-SiGe layer is disposed on the surface of the openings in the substrate. The second poly-SiGe layer is disposed on the first poly-SiGe layer, and the top of the second poly-SiGe layer is higher than the surface of the substrate. Moreover, the boron concentration in the first poly-SiGe layer is lower than that in the second poly-SiGe layer.

    摘要翻译： 提供半导体器件。 半导体器件包括衬底，栅极结构，间隔物，硼掺杂的第一多晶SiGe层和硼掺杂的第二多晶SiGe层。 基板具有两个开口，栅极结构设置在开口之间的基板上。 间隔件设置在栅极结构的侧壁上并在开口的一部分上方。 第一多晶硅层被设置在衬底中的开口的表面上。 第二多晶SiGe层设置在第一多晶硅层上，第二多晶硅层的顶部高于衬底的表面。 此外，第一多晶SiGe层中的硼浓度低于第二多晶硅层中的硼浓度。

    Method of fabricating gates
    8.
    发明授权
    Method of fabricating gates 有权
    制造门的方法

    公开(公告)号：US07186605B2

    公开(公告)日：2007-03-06

    申请号：US11016050

    申请日：2004-12-17

    申请人： Po-Lun Cheng ,  Li-Wei Cheng

    发明人： Po-Lun Cheng ,  Li-Wei Cheng

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/823842

    摘要： A method of fabricating gates is provided. A first sacrificial layer having a first and a second gate openings therein is formed on a substrate. Next, a gate dielectric layer is formed on the substrate exposed by the first sacrificial layer. Thereafter, a second sacrificial layer is filled in the first and second gate openings. The second sacrificial layer in the first gate opening is removed, and then a first conductive layer is filled in the first gate opening as a gate of a MOS transistor of a first conductivity type. Then, the second sacrificial layer in the second gate opening is removed. A second conductive layer is filled in the second gate opening as a gate of a MOS transistor of a second conductivity type, and the first sacrificial layer is removed.

    摘要翻译： 提供一种制造栅极的方法。 在基板上形成有第一和第二栅极开口的第一牺牲层。 接下来，在由第一牺牲层露出的基板上形成栅极电介质层。 此后，在第一和第二栅极开口中填充第二牺牲层。 去除第一栅极开口中的第二牺牲层，然后在第一栅极开口中填充第一导电层作为第一导电类型的MOS晶体管的栅极。 然后，去除第二门开口中的第二牺牲层。 在第二栅极开口中填充第二导电层作为第二导电类型的MOS晶体管的栅极，并且去除第一牺牲层。

    Complementary metal-oxide-semiconductor device and fabricating method thereof
    9.
    发明授权
    Complementary metal-oxide-semiconductor device and fabricating method thereof 有权
    互补金属氧化物半导体器件及其制造方法

    公开(公告)号：US07402496B2

    公开(公告)日：2008-07-22

    申请号：US11530480

    申请日：2006-09-11

    申请人： Che-Hung Liu ,  Po-Lun Cheng ,  Chun-An Lin ,  Li-Yuen Tang ,  Hung-Lin Shih ,  Ming-Chi Fan ,  Hsien-Liang Meng ,  Jih-Shun Chiang

    发明人： Che-Hung Liu ,  Po-Lun Cheng ,  Chun-An Lin ,  Li-Yuen Tang ,  Hung-Lin Shih ,  Ming-Chi Fan ,  Hsien-Liang Meng ,  Jih-Shun Chiang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

    摘要： A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

    摘要翻译： 互补金属氧化物半导体（CMOS）器件包括具有第一有源区和第二有源区的衬底; 分别设置在所述第一有源区和所述第二有源区上的第一栅极结构和第二栅极结构; 分别设置在第一栅极结构和第二栅极结构的侧壁上的第一间隔结构和第二间隔结构; 在第一栅极结构和第二栅极结构的两侧分别设置在基板中的第一LDD和第二LDD; 外延材料层，设置在第一有源区并位于第一LDD的一侧; 以及钝化层，设置在所述第一栅极结构上，所述第一间隔结构和所述第一LDD并且覆盖所述第二有源区，其中所述钝化层包含含碳氮氧化物层。

    COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE
    10.
    发明申请
    COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE 审中-公开
    补充金属氧化物半导体器件

    公开(公告)号：US20080116525A1

    公开(公告)日：2008-05-22

    申请号：US12024069

    申请日：2008-01-31

    申请人： Che-Hung Liu ,  Po-Lun Cheng ,  Chun-An Lin ,  Li-Yuen Tang ,  Hung-Lin Shih ,  Ming-Chi Fan ,  Hsien-Liang Meng ,  Jih-Shun Chiang

    发明人： Che-Hung Liu ,  Po-Lun Cheng ,  Chun-An Lin ,  Li-Yuen Tang ,  Hung-Lin Shih ,  Ming-Chi Fan ,  Hsien-Liang Meng ,  Jih-Shun Chiang

    IPC分类号： H01L27/088

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

    摘要： A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

    摘要翻译： 互补金属氧化物半导体（CMOS）器件包括具有第一有源区和第二有源区的衬底; 分别设置在所述第一有源区和所述第二有源区上的第一栅极结构和第二栅极结构; 分别设置在第一栅极结构和第二栅极结构的侧壁上的第一间隔结构和第二间隔结构; 在第一栅极结构和第二栅极结构的两侧分别设置在基板中的第一LDD和第二LDD; 外延材料层，设置在第一有源区并位于第一LDD的一侧; 以及钝化层，设置在所述第一栅极结构上，所述第一间隔结构和所述第一LDD并且覆盖所述第二有源区，其中所述钝化层包含含碳氮氧化物层。