公开(公告)号：US06140201A

公开(公告)日：2000-10-31

申请号：US172407

申请日：1998-10-14

申请人： J. S. Jason Jenq ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Chuan-Fu Wang

发明人： J. S. Jason Jenq ,  Sun-Chieh Chien ,  Der-Yuan Wu ,  Chuan-Fu Wang

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/92 ,  H01L21/3143 ,  H01L27/10852

摘要： A method for fabricating a cylinder capacitor of a DRAM cell that starts with forming a first oxide layer and then a doped first polysilicon layer on a substrate, patterning the first polysilicon layer to form a first opening that exposes the first oxide layer, forming a polysilicon spacer at the laterals of the first opening. Then, a portion of the first oxide layer is removed to expose the substrate by using the polysilicon spacer and the first polysilicon layer as a mask. A doped second polysilicon layer is formed on the first polysilicon layer and in the first opening. A portion of the second polysilicon layer is removed to form a second opening. A oxide spacer is formed on the laterals of the second opening, and is used as mask to remove a portion of the second polysilicon layer for forming a lower electrode. A dielectric layer and then a third polysilicon layer are formed on the lower electrode after the silicon oxide spacer is removed, wherein the third polysilicon is an upper electrode.

摘要翻译： 一种用于制造DRAM单元的圆柱电容器的方法，其开始于形成第一氧化物层，然后在衬底上形成掺杂的第一多晶硅层，图案化第一多晶硅层以形成暴露第一氧化物层的第一开口，形成多晶硅 间隔在第一个开口的边缘。 然后，通过使用多晶硅间隔物和第一多晶硅层作为掩模，去除第一氧化物层的一部分以暴露衬底。 掺杂的第二多晶硅层形成在第一多晶硅层和第一开口中。 去除第二多晶硅层的一部分以形成第二开口。 在第二开口的侧壁上形成氧化物间隔物，并且用作掩模以去除用于形成下电极的第二多晶硅层的一部分。 在除去氧化硅间隔物之后，在下电极上形成电介质层，然后形成第三多晶硅层，其中第三多晶硅是上电极。

公开(公告)号：US6124166A

公开(公告)日：2000-09-26

申请号：US340401

申请日：1999-06-28

申请人： Chuan-Fu Wang ,  Der-Yuan Wu

发明人： Chuan-Fu Wang ,  Der-Yuan Wu

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/84 ,  H01L28/91 ,  H01L27/10852

摘要： The present invention relates to a method of forming a lower electrode of a capacitor on a DRAM cell in a semiconductor wafer for increasing a surface area of the lower electrode. It is achieved by forming a second dielectric layer on a first polysilicon layer which comprises a plurality of doped horizontal layers along a vertical direction. Because dopant densities of the doped horizontal layers alternate in a high and low sequence, when forming a second polysilicon layer on the second dielectric layer, the second polysilicon layer will have many hemispherical grains on the vertical side wall of the second dielectric layer. This will result in an increased surface area of the lower electrode.

摘要翻译： 本发明涉及在用于增加下电极的表面积的半导体晶片中的DRAM单元上形成电容器的下电极的方法。 通过在第一多晶硅层上形成第二介质层来实现，该第一多晶硅层包括沿着垂直方向的多个掺杂的水平层。 由于掺杂水平层的掺杂浓度以高和低顺序交替，所以当在第二介电层上形成第二多晶硅层时，第二多晶硅层将在第二介电层的垂直侧壁上具有许多半球形晶粒。 这将导致下电极的表面积增加。

公开(公告)号：US5913129A

公开(公告)日：1999-06-15

申请号：US5554

申请日：1998-01-12

申请人： Der-Yuan Wu ,  Chuan-Fu Wang

发明人： Der-Yuan Wu ,  Chuan-Fu Wang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L27/10814 ,  H01L28/84 ,  H01L28/90 ,  H01L28/91

摘要： A method of fabricating a capacitor structure for a dynamic random access memory. This method comprises the following steps: a transistor is provided on a semiconductor substrate, and spacers are formed over the sidewalls of a gate electrode of the transistor. A first oxide layer is formed over the transistor. A bit line is deposited to contact with the source region of the transistor. Thereafter, a second oxide layer is formed over the bit line. A contact opening is formed exposing the drain region. Then the hemispherical grained silicon layer is formed into the contact opening. A polysilicon layer is formed over the hemispherical grained silicon layer. Therefore both the hemispherical grained silicon layer and the third polysilicon layer have rough surfaces. Subsequent conventional processes for the complete formation of capacitor structure are performed. It is therefore the capacitor maintains a required capacitance while reducing the horizontal dimensions of the storage capacitor.

摘要翻译： 一种制造用于动态随机存取存储器的电容器结构的方法。 该方法包括以下步骤：在半导体衬底上设置晶体管，并且在晶体管的栅电极的侧壁上形成间隔物。 第一氧化物层形成在晶体管上。 沉积位线以与晶体管的源极区域接触。 此后，在位线上形成第二氧化物层。 形成露出漏区的接触开口。 然后将半球状粒状硅层形成为接触开口。 在半球形晶粒硅层上形成多晶硅层。 因此，半球状的硅层和第三多晶硅层都具有粗糙的表面。 执行用于完全形成电容器结构的随后的常规方法。 因此，电容器保持所需的电容，同时减小存储电容器的水平尺寸。

公开(公告)号：US07335933B2

公开(公告)日：2008-02-26

申请号：US10718896

申请日：2003-11-20

申请人： Yung-Chang Lin ,  Chia-Wen Liang ,  Chuan-Fu Wang

发明人： Yung-Chang Lin ,  Chia-Wen Liang ,  Chuan-Fu Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/10832 ,  H01L27/10867 ,  H01L29/66181

摘要： A DRAM cell and a method for fabricating the same are provided. The method includes: forming a trench in a substrate; forming a first capacitor dielectric layer on the surface of the trench; forming a conducting layer inside the trench; forming a second capacitor dielectric layer on the surface of the substrate and on the conducting layer, wherein the substrate around the first and second capacitor dielectric layers serves as a bottom electrode; forming a protruding electrode on the substrate, the protruding electrode being on the substrate around the trench and covering a junction between the trench and the substrate; and electrically connecting the protruding electrode and the conducting layer, the conducting layer and the protruding electrode being an upper electrode.

摘要翻译： 提供DRAM单元及其制造方法。 该方法包括：在衬底中形成沟槽; 在所述沟槽的表面上形成第一电容器电介质层; 在沟槽内形成导电层; 在所述衬底的表面上和所述导电层上形成第二电容器电介质层，其中所述第一和第二电容器电介质层周围的衬底用作底部电极; 在所述基板上形成突出电极，所述突出电极位于所述基板周围，并且覆盖所述沟槽和所述基板之间的接合部; 并且将所述突出电极和所述导电层电连接，所述导电层和所述突出电极为上电极。

公开(公告)号：US06326276B1

公开(公告)日：2001-12-04

申请号：US09371414

申请日：1999-08-10

申请人： King-Lung Wu ,  Chuan-Fu Wang

发明人： King-Lung Wu ,  Chuan-Fu Wang

IPC分类号： H01L2120

CPC分类号： H01L28/92

摘要： A method for forming a capacitor in DRAM is disclosed. The method includes: providing a conductor defined on a first dielectric layer; forming a second dielectric layer on the conductor; then forming a polysilicon layer on the second dielectric layer, the polysilicon layer serves as an etching mask; next, etching the second dielectric layer; removing said polysilicon layer; etching said conductor; and finally removing said second dielectric layer.

摘要翻译： 公开了一种在DRAM中形成电容器的方法。 该方法包括：提供限定在第一电介质层上的导体; 在导体上形成第二电介质层; 然后在第二介电层上形成多晶硅层，多晶硅层用作蚀刻掩模; 接下来，蚀刻第二介电层; 去除所述多晶硅层; 蚀刻所述导体; 最后移除所述第二电介质层。

公开(公告)号：US06207581B1

公开(公告)日：2001-03-27

申请号：US09387094

申请日：1999-09-01

申请人： King-Lung Wu ,  Chuan-Fu Wang

发明人： King-Lung Wu ,  Chuan-Fu Wang

IPC分类号： H01L2100

CPC分类号： H01L21/76802

摘要： A method of fabricating a node contact hole is disclosed. The fabrication includes the steps as follows. At first, the first interpoly dielectric (IPD1) layer is formed over the semiconductor substrate. The landing pad is formed in the first interpoly dielectric layer. The polycide bit line is formed on the first interpoly dielectric layer. Afterwards, the second interpoly dielectric (IPD2) layer is formed over the first interpoly dielectric layer. Next, the defined photoresist layer is formed on the second interpoly dielectric layer, then using reflow and curing processes to form the heated photoresist layer. Afterwards, a portion of the second interpoly dielectric layer is firstly etched, using the heated photoresist layer as a mask. The depth is formed in the second interpoly dielectric layer. Then the heated photoresist layer is removed. Next, in order to the silicon nitride layer and the polysilicon layer are deposited over the second interpoly dielectric layer. Then, the polysilicon layer is etched back to expose the silicon nitride layer. Afterwards, a portion of the second interpoly dielectric layer is secondly etched to expose the land pad. Next, in order to the polysilicon layer and the silicon nitride layer are removed over the second interpoly dielectric layer. The node contact hole is formed in the second interpoly dielectric layer.

摘要翻译： 公开了一种制造节点接触孔的方法。 该制造包括以下步骤。 首先，在半导体衬底之上形成第一多晶硅间电介质（IPD1）层。 着陆焊盘形成在第一多余介电层中。 多晶硅位线形成在第一互聚电介质层上。 之后，第二互聚电介质（IPD2）层形成在第一层间介电层上。 接下来，将限定的光致抗蚀剂层形成在第二间隔电介质层上，然后使用回流和固化工艺形成加热的光致抗蚀剂层。 然后，使用加热的光致抗蚀剂层作为掩模，首先蚀刻第二互聚电介质层的一部分。 深度形成在第二互聚电介质层中。 然后去除加热的光致抗蚀剂层。 接下来，为了使氮化硅层和多晶硅层沉积在第二间隔电介质层上。 然后，将多晶硅层回蚀以暴露氮化硅层。 之后，第二次间电介质层的一部分被二次蚀刻以露出焊盘。 接下来，为了将多晶硅层和氮化硅层去除在第二互聚电介质层上。 节点接触孔形成在第二互聚电介质层中。

公开(公告)号：US5879987A

公开(公告)日：1999-03-09

申请号：US79253

申请日：1998-05-14

申请人： Chuan-Fu Wang

发明人： Chuan-Fu Wang

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A structure of a capacitor in a DRAM includes: A dielectric layer with a contact window for later connecting use is formed on a substrate. Then, a first-conductive layer is formed over the dielectric and is coupled to either the source or the drain of a TFET through the contact window. Subsequently, a number of insulating layers and second-conductive layers are superposed alternatively together to form a stacked layer. By using the space occupied by the insulating layers, a number of third-conductive layers replacing the inner portion of the insulating layers are formed in between the second-conductive layers. After removing the insulating layers between the second-conductive layers, a structure of a horn-like in a sectional view is formed. The first-conductive layer, the second-conductive layers and the third-conductive layers are coupled together to act as a lower electrode of the capacitor. Then, a dielectric thin film is formed over the lower electrode. And then, the fourth-conductive layer is formed over the dielectric thin film to act as an upper electrode.

摘要翻译： DRAM中的电容器的结构包括：在基板上形成具有用于稍后连接使用的接触窗的电介质层。 然后，在电介质上形成第一导电层，并通过接触窗口与TFET的源极或漏极耦合。 随后，将多个绝缘层和第二导电层交替叠加在一起以形成堆叠层。 通过使用由绝缘层占据的空间，在第二导电层之间形成有代替绝缘层的内部的多个第三导体层。 在去除第二导电层之间的绝缘层之后，形成截面图中的喇叭状的结构。 第一导电层，第二导电层和第三导电层耦合在一起以用作电容器的下电极。 然后，在下电极上形成电介质薄膜。 然后，第四导电层形成在电介质薄膜上，用作上电极。

公开(公告)号：US06368908B1

公开(公告)日：2002-04-09

申请号：US09200242

申请日：1998-11-25

申请人： Chuan-Fu Wang ,  J. S. Jason Jenq

发明人： Chuan-Fu Wang ,  J. S. Jason Jenq

IPC分类号： H01L218234

CPC分类号： H01L28/87 ,  H01L28/91

摘要： A method of fabricating a capacitor includes formation of a stacked layer formed by alternately forming conductive layers and isolation layers and then patterning these layers to form a stacked layer. An opening is formed above the source/drain region. A conductive spacer is formed on the sidewall of the opening. The conductive spacer is used as a mask. The dielectric layer below the stacked layer exposed by the opening is removed to form a contact hole. The top isolation layer of the stacked layer is removed. A conductive layer is formed over the substrate to fill the contact hole. The conductive spacer is covered by the conductive layer to form a raised region. A stacked spacer is formed beside the raised region. The isolation spacers of the stacked spacer and the isolation layer are removed to expose a storage electrode.

摘要翻译： 制造电容器的方法包括形成通过交替地形成导电层和隔离层形成的堆叠层，然后对这些层进行图案化以形成堆叠层。 在源极/漏极区域上形成开口。 在开口的侧壁上形成导电间隔物。 导电间隔物用作掩模。 去除由开口暴露的堆叠层下方的电介质层，形成接触孔。 去除堆叠层的顶部隔离层。 在衬底上形成导电层以填充接触孔。 导电间隔物被导电层覆盖以形成凸起区域。 在凸起区域旁边形成层叠间隔物。 去除层叠间隔物和隔离层的隔离间隔物以暴露存储电极。

公开(公告)号：US6096620A

公开(公告)日：2000-08-01

申请号：US191490

申请日：1998-11-13

申请人： Chuan-Fu Wang

发明人： Chuan-Fu Wang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L28/87

摘要： A method of fabricating a capacitor. Isolation layers and conductive layers are formed alternately on a dielectric layer on a substrate. The conductive layers and the isolation layers are patterned to form an opening to expose a conductive region of the substrate. A spacer is formed on the sidewall of the conductive layers and the isolation layers exposed by the opening. The spacer is used as a mask to form a contact hole. The conductive layer on the dielectric layer is used as an etching stop layer. The isolation layers and the conductive layers are patterned. A conductive layer is formed to cover the substrate to cover the isolation layers and the conductive layers and to fill the contact hole. A portion of the conductive layers is removed to expose the spacer. The spacer and isolation layers are removed to expose the storage electrode formed by the conductive layers. A dielectric film layer and a cell electrode are formed in sequence over the substrate.

摘要翻译： 一种制造电容器的方法。 隔离层和导电层交替地形成在基板上的电介质层上。 图案化导电层和隔离层以形成露出基板的导电区域的开口。 在导电层的侧壁和由开口露出的隔离层上形成间隔物。 间隔件用作掩模以形成接触孔。 电介质层上的导电层用作蚀刻停止层。 隔离层和导电层被图案化。 形成导电层以覆盖衬底以覆盖隔离层和导电层并填充接触孔。 导电层的一部分被去除以露出间隔物。 去除间隔物和隔离层以暴露由导电层形成的存储电极。 在衬底上依次形成电介质膜层和电池电极。

公开(公告)号：US6080619A

公开(公告)日：2000-06-27

申请号：US85903

申请日：1998-05-27

申请人： Sun-Chieh Chien ,  King-Lung Wu ,  Chuan-Fu Wang ,  Jason Jenq

发明人： Sun-Chieh Chien ,  King-Lung Wu ,  Chuan-Fu Wang ,  Jason Jenq

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90

摘要： A method for manufacturing a DRAM capacitor is provided to form a lower electrode with a cylindrical profile by using a first stage and a second stage. The stages provide different etching rates in various situations. The invention uses the stages to allow the part of the second polysilicon layer between the capacitors to be completely etched and prevent the other part of the second polysilicon layer serving as a lower electrode from over-etching. The invention provides an easier process of forming a cylindrical capacitor with a larger surface.

摘要翻译： 提供一种用于制造DRAM电容器的方法，以通过使用第一级和第二级形成具有圆柱形轮廓的下电极。 这些阶段在各种情况下提供不同的蚀刻速率。 本发明使用这些阶段来允许电容器之间的第二多晶硅层的一部分被完全蚀刻，并且防止用作下部电极的第二多晶硅层的另一部分过度蚀刻。 本发明提供了形成具有更大表面的圆柱形电容器的更容易的工艺。