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    Semiconductor integrated circuit device with test element group circuit
    2.
    发明申请
    Semiconductor integrated circuit device with test element group circuit 有权
    具有测试元件组电路的半导体集成电路器件

    公开(公告)号：US20050056834A1

    公开(公告)日：2005-03-17

    申请号：US10976491

    申请日：2004-10-30

    申请人： Chul-Sung Park ,  Yong-Hwan Noh ,  Byong-Kwon Lee ,  Hyang-Ja Yang

    发明人： Chul-Sung Park ,  Yong-Hwan Noh ,  Byong-Kwon Lee ,  Hyang-Ja Yang

    IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L23/544 ,  H01L23/58

    CPC分类号： H01L22/34 ,  G01R31/2884

    摘要： Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.

    摘要翻译： 公开了一种半导体集成电路器件，其包括连接在第一和第二焊盘之间的测试元件组电路。 测试元件组电路包括串联连接在第一和第二焊盘之间的多个半导体器件。 至少两个相邻的半导体器件通过由多层互连结构形成的信号路径相互连接。

    Semiconductor integrated circuit device with test element group circuit
    3.
    发明授权
    Semiconductor integrated circuit device with test element group circuit 有权
    具有测试元件组电路的半导体集成电路器件

    公开(公告)号：US06822330B2

    公开(公告)日：2004-11-23

    申请号：US10346019

    申请日：2003-01-16

    申请人： Chul-Sung Park ,  Yong-Hwan Noh ,  Byong-Kwon Lee ,  Hyang-Ja Yang

    发明人： Chul-Sung Park ,  Yong-Hwan Noh ,  Byong-Kwon Lee ,  Hyang-Ja Yang

    IPC分类号： H01L2348

    CPC分类号： H01L22/34 ,  G01R31/2884

    摘要： Disclosed is a semiconductor integrated circuit device which includes a test element group circuit connected between a first and a second pad. The test element group circuit includes a plurality of semiconductor devices connected in series between the first and second pads. At least two adjacent ones of the semiconductor devices are connected to each other via a signal path that is formed by a multi-layer interconnection structure.

    摘要翻译： 公开了一种半导体集成电路器件，其包括连接在第一和第二焊盘之间的测试元件组电路。 测试元件组电路包括串联连接在第一和第二焊盘之间的多个半导体器件。 至少两个相邻的半导体器件通过由多层互连结构形成的信号路径相互连接。

    Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits
    4.
    发明授权
    Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits 有权
    具有用于测试存储器阵列和外围电路的内部电压发生器的半导体存储器件

    公开(公告)号：US06958947B2

    公开(公告)日：2005-10-25

    申请号：US10359075

    申请日：2003-02-06

    申请人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

    发明人： Chul-Sung Park ,  Hyang-Ja Yang ,  Seung-Min Lee ,  Yong-Hwan Noh

    IPC分类号： G11C5/14 ,  G11C29/12 ,  G11C29/50

    CPC分类号： G11C29/12005 ,  G11C5/147 ,  G11C11/41 ,  G11C29/12 ,  G11C29/50 ,  G11C2207/2254

    摘要： A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.

    摘要翻译： 一种半导体存储器件，包括用于调节外部电源电压并产生第一和第二内部电源电压的内部电压发生器电路。 第一内部电源电压经由第一电源线提供给存储单元阵列，并且第二内部电源电压经由第二电源线提供给外围电路。 控制电路控制内部电压发生器电路，使得第一和第二内部电源电压的电平根据操作模式而变化。

    Semiconductor integrated circuit comprising functional modes
    5.
    发明授权
    Semiconductor integrated circuit comprising functional modes 失效
    半导体集成电路包括功能模式

    公开(公告)号：US06949960B2

    公开(公告)日：2005-09-27

    申请号：US10635253

    申请日：2003-08-06

    申请人： Chul-Sung Park ,  Hyang-Ja Yang ,  Hong-Kyun Kim ,  Yong-Hwan Noh

    发明人： Chul-Sung Park ,  Hyang-Ja Yang ,  Hong-Kyun Kim ,  Yong-Hwan Noh

    IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R23/02

    CPC分类号： G01R31/3172 ,  G01R31/31701

    摘要： An integrated circuit device includes a pin for receiving a DC voltage component signal. The device includes a signal source for applying an AC signal to the pin, a buffer for converting the AC signal into a digital signal, and a digital detector for detecting a frequency of the digital signal and outputting a predetermined detection signal. The predetermined detection signal is activated when the frequency of the digital signal is greater than or equal to a predetermined frequency. The predetermined detection signal is used as a signal for setting predetermined functional modes. The device further includes registers or a differential amplifier and a decoder for generating a plurality of functional mode signals.

    摘要翻译： 集成电路器件包括用于接收直流电压分量信号的引脚。 该装置包括用于向引脚施加AC信号的信号源，用于将AC信号转换为数字信号的缓冲器，以及用于检测数字信号频率并输出预定检测信号的数字检测器。 当数字信号的频率大于或等于预定频率时，预定的检测信号被激活。 预定检测信号用作设定预定功能模式的信号。 该装置还包括用于产生多个功能模式信号的寄存器或差分放大器和解码器。

    Level shifter and semiconductor device having off-chip driver
    6.
    发明授权
    Level shifter and semiconductor device having off-chip driver 失效
    具有片外驱动器的电平移位器和半导体器件

    公开(公告)号：US07902871B2

    公开(公告)日：2011-03-08

    申请号：US12759252

    申请日：2010-04-13

    申请人： Yong-Hwan Noh ,  Chul-Sung Park

    发明人： Yong-Hwan Noh ,  Chul-Sung Park

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018528

    摘要： Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

    摘要翻译： 提供了一种电平转换器和具有使用其的片外驱动器（OCD）的半导体器件。 电平移位器包括多个串联连接的逻辑门，其接收具有第一电源电压电平的第一状态输入信号，并产生具有第二电源电压电平的电平移位的第一状态输出信号。 逻辑门作为电源电压接收至少一个中间电源电压，其具有在第一电源电压电平和第二电源电压电平之间的中间的至少一个电压电平，并且施加到本逻辑门的中间电源电压为 等于或高于施加到先前逻辑门的中间电源电压。

    Method and apparatus for read operation and write operation in semiconductor memory device
    7.
    发明授权
    Method and apparatus for read operation and write operation in semiconductor memory device 有权
    用于半导体存储器件中的读操作和写操作的方法和装置

    公开(公告)号：US06674686B2

    公开(公告)日：2004-01-06

    申请号：US10037906

    申请日：2001-11-09

    申请人： Yong-Hwan Noh ,  Young-Ho Suh

    发明人： Yong-Hwan Noh ,  Young-Ho Suh

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C2207/107

    摘要： Methods and apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. Read and write operations are sequentially performed in a same cycle using QDR2 (Quadruple Data Rate 2) wherein each of the input and output modes operate at a 2-bit burst mode and a double data rate (DDR) mode, thereby minimizing cycle time or read and write operations are sequentially performed in a same cycle using QDR4 (Quadruple Data Rate 4), wherein each of the input and output modes operate at a 4-bit burst mode and a DDR mode, thereby minimizing the cycle time. In another aspect, when a read command is input in one cycle, a read operation is performed in synchronization with a rising edge of clock and a write operation is performed in synchronization with a signal that operates during the read operation.

    摘要翻译： 在包括独立数据输入总线和数据输出总线的I / O（输入/输出）架构的半导体存储器件中执行读和写操作的方法和装置。 使用QDR2（四倍数据速率2）在相同周期中顺序地执行读写操作，其中每个输入和输出模式以2位突发模式和双倍数据速率（DDR）模式操作，从而最小化周期时间或 使用QDR4（四倍数据速率4）在相同周期中顺序地执行读和写操作，其中每个输入和输出模式以4位突发模式和DDR模式操作，从而最小化循环时间。 在另一方面，当在一个周期中输入读取命令时，与时钟的上升沿同步地执行读取操作，并且与在读取操作期间操作的信号同步地执行写入操作。

    Internal clock generating circuit of synchronous type semiconductor memory device and method thereof
    8.
    发明授权
    Internal clock generating circuit of synchronous type semiconductor memory device and method thereof 有权
    同步型半导体存储器件的内部时钟发生电路及其方法

    公开(公告)号：US06269050B1

    公开(公告)日：2001-07-31

    申请号：US09594888

    申请日：2000-06-14

    申请人： Kook-Hwan Kwon ,  Yong-Hwan Noh

    发明人： Kook-Hwan Kwon ,  Yong-Hwan Noh

    IPC分类号： G11C800

    CPC分类号： G11C7/222 ,  G11C7/22

    摘要： An internal clock generating circuit of a synchronous type semiconductor memory device includes a transmission part for transmitting a first clock enable signal in response to applying a first level of a first clock signal. It also includes a latch part for latching the first clock enable signal transmitted from the transmission part. A gating part gates the latched first clock enable signal with the first clock signal to generate a second clock signal as an internal clock signal for the memory device. This reduces a time lag by which the speed of the internal clock is synchronized with the external clock signal.

    摘要翻译： 同步型半导体存储器件的内部时钟发生电路包括用于响应于施加第一电平的第一时钟信号而发送第一时钟使能信号的发送部分。 它还包括用于锁存从发送部分发送的第一时钟使能信号的锁存部分。 门控部分利用第一时钟信号对锁存的第一时钟使能信号进行门控，以产生作为存储器件的内部时钟信号的第二时钟信号。 这减少了内部时钟的速度与外部时钟信号同步的时滞。

    Synchronous semiconductor memory device and method for operating same
    9.
    发明授权
    Synchronous semiconductor memory device and method for operating same 有权
    同步半导体存储器件及其操作方法

    公开(公告)号：US06483770B2

    公开(公告)日：2002-11-19

    申请号：US09849289

    申请日：2001-05-04

    申请人： Yong-Hwan Noh ,  Kyo-Min Sohn

    发明人： Yong-Hwan Noh ,  Kyo-Min Sohn

    IPC分类号： G11C800

    CPC分类号： G11C7/1039 ,  G11C7/1072

    摘要： Disclosed is a semiconductor memory device comprising a pipeline structure having a sense amplifier responsive to a first enable signal; a data register responsive to a second enable signal for latching an output of said sense amplifier between said sense amplifier and a common data line; and a monitoring part to monitor said first and second enable signals and adapted to prevent overlapping between an enabling interval of said first enable signal and said second enable signal.

    摘要翻译： 公开了一种半导体存储器件，其包括具有响应于第一使能信号的读出放大器的流水线结构; 响应于第二使能信号的数据寄存器，用于锁存所述读出放大器与公共数据线之间的所述读出放大器的输出; 以及监视部分，用于监视所述第一和第二使能信号并适于防止所述第一使能信号的使能间隔和所述第二使能信号之间的重叠。

    Semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without a dead cycle
    10.
    发明授权
    Semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without a dead cycle 有权
    半导体存储器件能够在没有死循环的情况下接收到写入命令后执行1或2个周期的写入操作

    公开(公告)号：US06549994B1

    公开(公告)日：2003-04-15

    申请号：US09346286

    申请日：1999-07-01

    申请人： Yong-Hwan Noh

    发明人： Yong-Hwan Noh

    IPC分类号： G06F1200

    CPC分类号： G11C7/1039 ,  G11C7/1072 ,  G11C8/00 ,  G11C11/418 ,  G11C11/419

    摘要： The present invention relates to a semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without necessitating a dead cycle. The elimination of the dead cycle between read and write operations improves bus efficiency and thus, speed. The memory device of the present invention includes an address input control means for receiving an external write or read address and delaying the write address by either 1 or 2 cycles. A data input control means receives external write data and delays the write data by a first or second predetermined number of cycles according to the write mode. A data transmission control means transmits the delayed write data responsive to a predetermined set of input commands. The data input control means reads the data from a cell corresponding to the read address, provides the write data to a cell corresponding to the write address, and writes the transmitted delayed data into the cell corresponding to the write address.

    摘要翻译： 本发明涉及一种半导体存储器件，其能够在不需要死循环的情况下在接收到写入命令之后执行1或2个周期的写入操作。 在读写操作之间消除死循环可以提高总线效率，从而提高速度。 本发明的存储装置包括地址输入控制装置，用于接收外部写入或读取地址并延迟写入地址1或2个周期。 数据输入控制装置接收外部写入数据，并根据写入模式将写入数据延迟第一或第二预定次数的周期。 数据传输控制装置响应于预定的一组输入命令发送延迟的写入数据。 数据输入控制装置从与读取地址相对应的单元读取数据，将写入数据提供给与写入地址相对应的单元，并将发送的延迟数据写入与写入地址对应的单元。