公开(公告)号：US20110228582A1

公开(公告)日：2011-09-22

申请号：US13024566

申请日：2011-02-10

申请人： Chul-Woo PARK ,  Hong-Sun HWANG ,  In-Gyu BAEK ,  Dong-Hyun SOHN

发明人： Chul-Woo PARK ,  Hong-Sun HWANG ,  In-Gyu BAEK ,  Dong-Hyun SOHN

IPC分类号： G11C5/02 ,  G11C5/06 ,  H01L27/24 ,  H01L21/77

CPC分类号： H01L21/77 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/24

摘要： A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.

摘要翻译： 叠层半导体存储器件包括具有功能电路，多个存储单元阵列层以及至少一个连接层的半导体衬底。 存储单元阵列层堆叠在半导体衬底之上。 连接层堆叠在半导体衬底之上，独立于存储单元阵列层。 连接层将布置在存储单元阵列层上的存储单元选择线电连接到功能电路。

公开(公告)号：US20090302302A1

公开(公告)日：2009-12-10

申请号：US12533793

申请日：2009-07-31

申请人： Jang-Eun HEO ,  Moon-Sook LEE ,  Young-Moon CHOI ,  In-Gyu BAEK ,  Yoon-Ho SON ,  Suk-Hun CHOI ,  Kyung-Rae BYUN

发明人： Jang-Eun HEO ,  Moon-Sook LEE ,  Young-Moon CHOI ,  In-Gyu BAEK ,  Yoon-Ho SON ,  Suk-Hun CHOI ,  Kyung-Rae BYUN

IPC分类号： H01L45/00 ,  H01L21/20

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0002 ,  G11C2213/35 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675

摘要： Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein.

摘要翻译： 公开了一种金属 - 金属氧化物电阻式存储器件，其包括设置在衬底中的下导电层图案。 绝缘层形成在衬底上，包括用于部分地暴露下导电层图案的上表面的接触孔。 接触孔填充有从下导电层图案生长的碳纳米管。 在碳纳米管和绝缘层上形成由2-组分材料制成的上电极和过渡金属氧化物层。 金属 - 金属氧化物电阻式存储器件适用于高集成度，并通过增加其中的电阻而以相对较小的功耗进行操作。

公开(公告)号：US20070041125A1

公开(公告)日：2007-02-22

申请号：US11552085

申请日：2006-10-23

申请人： Young-Ki HA ,  Jang-Eun LEE ,  Hyun-Jo KIM ,  Se-Chung OH ,  Jun-Soo BAE ,  In-Gyu BAEK

发明人： Young-Ki HA ,  Jang-Eun LEE ,  Hyun-Jo KIM ,  Se-Chung OH ,  Jun-Soo BAE ,  In-Gyu BAEK

IPC分类号： G11B5/17

CPC分类号： H01L43/12 ,  H01L43/08

摘要： There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

摘要翻译： 提供了一种磁性隧道结结构及其制造方法。 磁性隧道结结构包括依次形成在下电极上的下电极，下磁层图案和隧道层图案。 磁隧道结结构还包括依次形成在隧道层图案的一部分上的上磁层图案，缓冲层图案和上电极。 上部磁性层图案的侧壁由氧化的上部磁性层包围，缓冲层图案的侧壁由氧化的缓冲层包围。 可以通过氧化缓冲层来防止磁性隧道结区域中上部磁性层图案和下部磁性层图案的消耗。

公开(公告)号：US20060263289A1

公开(公告)日：2006-11-23

申请号：US11419986

申请日：2006-05-23

申请人： Jang-Eun HEO ,  Moon-Sook LEE ,  Young-Moon CHOI ,  In-Gyu BAEK ,  Yoon-Ho SON ,  Suk-Hun CHOI ,  Kyung-Rae BYUN

发明人： Jang-Eun HEO ,  Moon-Sook LEE ,  Young-Moon CHOI ,  In-Gyu BAEK ,  Yoon-Ho SON ,  Suk-Hun CHOI ,  Kyung-Rae BYUN

IPC分类号： D01F9/12

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0002 ,  G11C2213/35 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675

摘要： Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein.