公开(公告)号：US07439772B2

公开(公告)日：2008-10-21

申请号：US11154725

申请日：2005-06-15

申请人： Chul-Woo Park ,  Kyu-Hyoun Kim ,  Beom-Sig Cho

发明人： Chul-Woo Park ,  Kyu-Hyoun Kim ,  Beom-Sig Cho

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K19/00361

摘要： A level shifting circuit and method that reduce leakage current are provided. The level shifting circuit includes: a logic circuit including a plurality of MOSFETs (metal-oxide-semiconductor field effect transistors) connected in series between an output terminal and a source, receiving an input signal having a first logic level and a second logic level, changing the input signal to a signal having a first logic level and a third logic level in response to a feedback signal supplied to one of the MOSFETs, and outputting the changed signal as an output signal; and a feedback circuit generating the feedback signal in response to the output signal.

摘要翻译： 提供降低泄漏电流的电平移动电路和方法。 电平移位电路包括：逻辑电路，包括串联连接在输出端和源之间的多个MOSFET（金属氧化物半导体场效应晶体管），接收具有第一逻辑电平和第二逻辑电平的输入信号， 响应于提供给一个MOSFET的反馈信号，将输入信号改变为具有第一逻辑电平和第三逻辑电平的信号，并输出改变的信号作为输出信号; 以及响应于输出信号产生反馈信号的反馈电路。

公开(公告)号：US20060055424A1

公开(公告)日：2006-03-16

申请号：US11154725

申请日：2005-06-15

申请人： Chul-Woo Park ,  Kyu-Hyoun Kim ,  Beom-Sig Cho

发明人： Chul-Woo Park ,  Kyu-Hyoun Kim ,  Beom-Sig Cho

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K19/00361

摘要： A level shifting circuit and method that reduce leakage current are provided. The level shifting circuit includes: a logic circuit including a plurality of MOSFETs (metal-oxide-semiconductor field effect transistors) connected in series between an output terminal and a source, receiving an input signal having a first logic level and a second logic level, changing the input signal to a signal having a first logic level and a third logic level in response to a feedback signal supplied to one of the MOSFETs, and outputting the changed signal as an output signal; and a feedback circuit generating the feedback signal in response to the output signal.

摘要翻译： 提供降低泄漏电流的电平移动电路和方法。 电平移位电路包括：逻辑电路，包括串联连接在输出端和源之间的多个MOSFET（金属氧化物半导体场效应晶体管），接收具有第一逻辑电平和第二逻辑电平的输入信号， 响应于提供给一个MOSFET的反馈信号，将输入信号改变为具有第一逻辑电平和第三逻辑电平的信号，并输出改变的信号作为输出信号; 以及响应于输出信号产生反馈信号的反馈电路。

公开(公告)号：US20130135956A1

公开(公告)日：2013-05-30

申请号：US13483719

申请日：2012-05-30

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC分类号： G11C7/22

CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

摘要翻译： 存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。 时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。 数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。 相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。 相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。

公开(公告)号：US20110219248A1

公开(公告)日：2011-09-08

申请号：US12966039

申请日：2010-12-13

申请人： Beom-Sig Cho ,  Tae-Sik Son

发明人： Beom-Sig Cho ,  Tae-Sik Son

IPC分类号： G06F1/32

CPC分类号： G06F1/32

摘要： A power-down method for a system including a plurality of volatile memory devices is disclosed. The method includes providing some of the plurality of volatile memory devices or some memory regions of the volatile memory devices to operate in a self-refresh mode, thereby increasing a rebooting operation speed and reducing power consumption.

摘要翻译： 公开了一种用于包括多个易失性存储器件的系统的掉电方法。 该方法包括提供多个易失性存储器件中的一些或易失性存储器件的某些存储器区域以自刷新模式操作，由此增加重新启动操作速度并降低功耗。

公开(公告)号：US08725976B2

公开(公告)日：2014-05-13

申请号：US12983509

申请日：2011-01-03

申请人： Beom-Sig Cho ,  Jang-Seok Choi

发明人： Beom-Sig Cho ,  Jang-Seok Choi

IPC分类号： G06F12/00 ,  G06F11/22

CPC分类号： G06F15/18

摘要： In one embodiment, a method of performing data training in a system including a memory controller and at least a first memory device including a group of memory banks is disclosed. The method includes providing a plurality of enabling states for the group of memory banks, wherein each enabling state is different and for each enabling state a set of the memory banks of the group is enabled and any remaining of the memory banks of the group are not enabled. The method further includes performing a first data training procedure that includes a series of first data training operations for the first memory device, each data training operation being performed for a different one of the plurality of enabling states, generating a noise profile based on the series of first data training operations, statistically analyzing the noise profile to select a reference enabling state of the group of memory banks, and performing a second data training procedure for the first memory device using the reference enabling state. As a result, the operating speed and reliability of the system including the memory device may be improved.

摘要翻译： 在一个实施例中，公开了一种在包括存储器控制器和包括一组存储器组的至少第一存储器件的系统中执行数据训练的方法。 该方法包括为存储器组组提供多个使能状态，其中每个使能状态不同，并且对于每个使能状态，组的存储体组的一组被使能，并且该组的存储体的任何剩余部分不是 启用 该方法还包括执行第一数据训练程序，该程序包括针对第一存储器设备的一系列第一数据训练操作，针对多个使能状态中的不同一个执行每个数据训练操作，基于该系列产生噪声分布 对第一数据训练操作进行统计分析，以便选择存储器组组的参考使能状态，以及使用参考使能状态对第一存储器件执行第二数据训练程序。 结果，可以提高包括存储装置的系统的操作速度和可靠性。

公开(公告)号：US08499206B2

公开(公告)日：2013-07-30

申请号：US12966171

申请日：2010-12-13

申请人： Beom-Sig Cho ,  Jung-Joon Lee

发明人： Beom-Sig Cho ,  Jung-Joon Lee

IPC分类号： G06F11/00

CPC分类号： G06F11/00

摘要： A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented.

摘要翻译： 存储器系统包括具有错误计数器的错误检测电路。 当由错误计数器确定的误码率（BER）超过参考BER时，存储器系统通过调整其运行速度或工作电压，重新执行数据训练或阻抗匹配或调整数据摆幅宽度来降低BER。 因此，可以执行控制误码率的方法，并且防止系统挂起。

公开(公告)号：US08656199B2

公开(公告)日：2014-02-18

申请号：US12966039

申请日：2010-12-13

申请人： Beom-Sig Cho ,  Tae-Sik Son

发明人： Beom-Sig Cho ,  Tae-Sik Son

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/32

摘要： A power-down method for a system including a plurality of volatile memory devices is disclosed. The method includes providing some of the plurality of volatile memory devices or some memory regions of the volatile memory devices to operate in a self-refresh mode, thereby increasing a rebooting operation speed and reducing power consumption.

摘要翻译： 公开了一种用于包括多个易失性存储器件的系统的掉电方法。 该方法包括提供多个易失性存储器件中的一些或易失性存储器件的某些存储器区域以自刷新模式操作，由此增加重新启动操作速度并降低功耗。

公开(公告)号：US08335291B2

公开(公告)日：2012-12-18

申请号：US12929627

申请日：2011-02-04

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC分类号： H04L7/00

CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

摘要： A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.

摘要翻译： 提供半导体器件，并行接口系统及其方法。 示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号 传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号 与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息 在第二操作模式中的位信号和参考时钟信号。 示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜 在第二操作模式中参考信号和并行数据位信号之间的差异。

公开(公告)号：US20110219274A1

公开(公告)日：2011-09-08

申请号：US12966171

申请日：2010-12-13

申请人： Beom-Sig Cho ,  Jung-Joon Lee

发明人： Beom-Sig Cho ,  Jung-Joon Lee

IPC分类号： G06F11/00

CPC分类号： G06F11/00

摘要： A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented.

摘要翻译： 存储器系统包括具有错误计数器的错误检测电路。 当由错误计数器确定的误码率（BER）超过参考BER时，存储器系统通过调整其运行速度或工作电压，重新执行数据训练或阻抗匹配或调整数据摆幅宽度来降低BER。 因此，可以执行控制误码率的方法，并且防止系统挂起。

公开(公告)号：US08780668B2

公开(公告)日：2014-07-15

申请号：US13483719

申请日：2012-05-30

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

摘要翻译： 存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。 时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。 数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。 相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。 相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。