公开(公告)号：US06813204B2

公开(公告)日：2004-11-02

申请号：US10324406

申请日：2002-12-20

申请人： Chul-soo Kim ,  Young-hyun Jun ,  Jae-goo Lee

发明人： Chul-soo Kim ,  Young-hyun Jun ,  Jae-goo Lee

IPC分类号： G11C700

CPC分类号： G11C7/1084 ,  G11C7/1048

摘要： A semiconductor memory device having a circuit precharging a data line comprises a first precharge circuit, which precharges a first data line pair to a first voltage level in a precharge operation state, and a second precharge circuit, which precharges a second data line pair to a second voltage level in a precharge operation state. The semiconductor memory device comprises a data input driver, which receives data and drives the data to the first data line pair, a switch, which in response to a selection signal, connects or disconnects the first data line pair with the second data line pair, and a charge-sharing control circuit, which in response to the selection signal makes one line of the first data line pair and one line of the second data line pair share charge. The semiconductor memory device reduces current consumption over repeated write/precharge operations.

摘要翻译： 具有对数据线进行预充电的电路的半导体存储器件包括：第一预充电电路，其将第一数据线对预充电到预充电操作状态下的第一电压电平;以及第二预充电电路，其将第二数据线对预充电到 在预充电操作状态下的第二电压电平。 半导体存储器件包括数据输入驱动器，其接收数据并将数据驱动到第一数据线对;开关，其响应于选择信号将第一数据线对与第二数据线对连接或断开， 以及电荷共享控制电路，其响应于选择信号使得第一数据线对的一条线和第二数据线对的一条线共享电荷。 半导体存储器件通过重复的写入/预充电操作来减少电流消耗。

公开(公告)号：US07589580B2

公开(公告)日：2009-09-15

申请号：US11797865

申请日：2007-05-08

申请人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

发明人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： Provided are a reference current generating method and a current reference circuit. The reference current generating method includes generating a first current using a NMOS transistor and a second current using a PMOS transistor, calculating a current difference between the first and second currents, generating a third current which has a similar current/temperature slope as the second current by multiplying the current difference by a proportional constant, and generating a reference current by subtracting the third current from the second current.

摘要翻译： 提供了参考电流产生方法和电流参考电路。 参考电流产生方法包括使用NMOS晶体管产生第一电流和使用PMOS晶体管产生第二电流，计算第一和第二电流之间的电流差，产生具有与第二电流相似的电流/温度斜率的第三电流 通过将电流差乘以比例常数，并通过从第二电流减去第三电流来产生参考电流。

公开(公告)号：US20070273352A1

公开(公告)日：2007-11-29

申请号：US11797865

申请日：2007-05-08

申请人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

发明人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： Provided are a reference current generating method and a current reference circuit. The reference current generating method includes generating a first current using a NMOS transistor and a second current using a PMOS transistor, calculating a current difference between the first and second currents, generating a third current which has a similar current/temperature slope as the second current by multiplying the current difference by a proportional constant, and generating a reference current by subtracting the third current from the second current.

摘要翻译： 提供了参考电流产生方法和电流参考电路。 参考电流产生方法包括使用NMOS晶体管产生第一电流和使用PMOS晶体管产生第二电流，计算第一和第二电流之间的电流差，产生具有与第二电流相似的电流/温度斜率的第三电流 通过将电流差乘以比例常数，并通过从第二电流减去第三电流来产生参考电流。

公开(公告)号：US09093038B2

公开(公告)日：2015-07-28

申请号：US12784200

申请日：2010-05-20

申请人： Byung-hun Han ,  Jae-goo Lee

发明人： Byung-hun Han ,  Jae-goo Lee

IPC分类号： G09G3/36 ,  G09G3/32

CPC分类号： G09G3/3614 ,  G09G3/3648 ,  G09G3/3696 ,  G09G2330/02

摘要： A voltage stabilizer circuit for alternately or simultaneously stabilizing first and second generated voltages includes shared capacitor connected between the first and second generated voltages. The voltage stabilizer circuit may further include first and second switches for alternately connecting the first and second electrode of the shared capacitor to a ground. The alternation of the stabilized first and second voltages output by the voltage stabilizer circuit can be synchronized with a pixel polarity inversion mode signal output by the internal driver circuit of an LCD display.

摘要翻译： 用于交替或同时稳定第一和第二产生电压的稳压器电路包括连接在第一和第二产生电压之间的共享电容器。 电压稳定器电路还可以包括用于将共享电容器的第一和第二电极交替地连接到地的第一和第二开关。 由稳压器电路输出的稳定的第一和第二电压的交替可与由LCD显示器的内部驱动电路输出的像素极性反转模式信号同步。

公开(公告)号：US20090096731A1

公开(公告)日：2009-04-16

申请号：US12287069

申请日：2008-10-06

申请人： Jae-hyuck Woo ,  Jae-goo Lee

发明人： Jae-hyuck Woo ,  Jae-goo Lee

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2320/0271

摘要： A method and apparatus for generating gradation voltages are provided. Maximum and minimum reference voltages are selected from a distribution of voltages ranging from a first source voltage to a second source voltage. The maximum reference voltage is selected as a 1st gradation voltage and the minimum reference voltage is selected as an Nth gradation voltage, or vice versa, in response to an inversion control signal, where N is a natural number. First to Mth gamma voltages are selected from among a plurality of voltages generated by a voltage distribution between the 1st gradation voltage and the Nth gradation voltage. Second to (N−1)th gradation voltages are generated from a voltage distribution between the 1st gradation voltage and the Nth gradation voltage, using the 1st gamma voltage to the Mth gamma voltage, where M is a natural number.

摘要翻译： 提供了用于产生灰度电压的方法和装置。 最大和最小参考电压从范围从第一源电压到第二源电压的电压分布中选择。 选择最大参考电压作为第一灰度电压，并且响应于反转控制信号，将最小参考电压选择为第N灰度电压，反之亦然，其中N是自然数。 从第一灰度电压和第N灰度电压之间的电压分布产生的多个电压中选择第一至第M个伽马电压。 使用第一伽玛电压与第M个伽马电压，从第一灰度电压和第N灰度电压之间的电压分布产生第二至第（N-1）个灰度电压，其中M是自然数。

公开(公告)号：US20080180589A1

公开(公告)日：2008-07-31

申请号：US12014277

申请日：2008-01-15

申请人： Jae-hyuck Woo ,  Jae-goo Lee ,  Won-sik Kang

发明人： Jae-hyuck Woo ,  Jae-goo Lee ,  Won-sik Kang

IPC分类号： G02F1/1343

CPC分类号： G09G3/3614 ,  G09G3/3655 ,  G09G2310/0248 ,  G09G2310/0297 ,  G09G2320/02 ,  G09G2320/0247 ,  G09G2320/0252 ,  G09G2330/021

摘要： A liquid crystal display (LCD) that includes a plurality of pixels, a switch unit, and a gate line driving unit. Each of the pixels includes a liquid crystal capacitor having a pixel electrode and a common electrode, and the pixels are located at intersections of a plurality of gate lines and a plurality of source lines. The switch unit applies source line driving voltages having levels opposite to a common voltage applied to the common electrode, to the source lines. The gate line driving unit sequentially outputs via gate lines gate line driving voltages to control the source line driving voltages to be applied to the pixel electrodes of the pixels. The common voltage transits from a first level to a second level or vice versa at the boundary between a first half frame and a second half frame. At the first half frame, the switch unit applies the source line driving voltages to only odd-numbered source lines. At the second half frame, the switch unit applies the source line driving voltage to only even-numbered source lines.

摘要翻译： 包括多个像素的液晶显示器（LCD），开关单元和栅极线驱动单元。 每个像素包括具有像素电极和公共电极的液晶电容器，并且像素位于多条栅极线和多条源极线的交点处。 开关单元将具有与施加到公共电极的公共电压相反的电平的源极线驱动电压施加到源极线。 栅极线驱动单元通过栅极线依次输出栅极线驱动电压，以控制要施加到像素的像素电极的源极线驱动电压。 公共电压在第一半帧和第二半帧之间的边界处从第一电平转换到第二电平或反之亦然。 在前半帧，开关单元将源极线驱动电压施加到仅奇数源极线。 在第二半帧，开关单元将源极线驱动电压施加到仅偶数源极线。

公开(公告)号：US07365572B2

公开(公告)日：2008-04-29

申请号：US11250117

申请日：2005-10-13

申请人： Jae-goo Lee ,  Im-soo Kang

发明人： Jae-goo Lee ,  Im-soo Kang

IPC分类号： H03K19/0175

CPC分类号： H03K19/018585

摘要： Provided is a multi-path input buffer circuit, which passes a signal input to a semiconductor device through different paths in consideration of the voltage level of the input signal. The multi-path input buffer circuit includes an input buffer stage, which can be driven using one of at least two power supply voltages, outputs path signals by passing an input signal through at least two paths, selects and enables one of the path signals in response to a plurality of path selection signals, and maintains the rest of the path signals in a high impedance state. The buffer circuit also includes a level shifter, which shifts the voltage level of a signal output from the input buffer stage via the first path, and a first logic operation circuit, which operates in response to the output signal of the input buffer stage and a signal output from the level shifter.

摘要翻译： 提供了一种多路输入缓冲电路，其考虑到输入信号的电压电平，将通过不同路径的信号输入到半导体器件。 多路输入缓冲器电路包括可以使用至少两个电源电压之一驱动的输入缓冲器级，通过使输入信号通过至少两条路径来输出路径信号，选择并启用 响应于多个路径选择信号，并将其余路径信号保持在高阻抗状态。 缓冲电路还包括电平移位器，其通过第一路径移位从输入缓冲器级输出的信号的电压电平;以及第一逻辑运算电路，其响应于输入缓冲器级的输出信号和 来自电平转换器的信号输出。

公开(公告)号：US20080084406A1

公开(公告)日：2008-04-10

申请号：US11866650

申请日：2007-10-03

申请人： Won-sik Kang ,  Jae-goo Lee

发明人： Won-sik Kang ,  Jae-goo Lee

IPC分类号： G09G5/00

CPC分类号： G09G5/003 ,  G09G3/36 ,  G09G2320/08 ,  G09G2330/021 ,  G09G2330/04 ,  G09G2330/06 ,  G09G2360/18 ,  G09G2370/04

摘要： A method of automatically recovering bit values of a control register includes storing command data inputted from a host in the control register and a portion of a graphic RAM (GRAM), and while a scanning operation is performed by the GRAM, outputting the command data stored in the GRAM to the control register and refreshing the control register.

摘要翻译： 自动恢复控制寄存器的位值的方法包括存储从主机输入到控制寄存器中的命令数据和图形RAM（GRAM）的一部分，并且当由GRAM执行扫描操作时，输出存储的命令数据 在GRAM中控制寄存器并刷新控制寄存器。

公开(公告)号：US06819614B2

公开(公告)日：2004-11-16

申请号：US10309055

申请日：2002-12-04

申请人： Jae-goo Lee

发明人： Jae-goo Lee

IPC分类号： G11C702

CPC分类号： G11C7/1069 ,  G11C7/065 ,  G11C7/1051 ,  G11C11/4096 ,  G11C2207/002

摘要： A semiconductor memory device having a more stable input/output (I/O) line sensing control scheme regardless of variation of a threshold voltage and a sensing control method thereof. The semiconductor memory device includes a control circuit that controls a pair of switch transistors which are connected between a pair of I/O lines and a pair of data lines. The control circuit may generate a control signal that turns on one switch transistor while turning off the other switch transistor, and varies the voltage level of the control signal according to variation of the threshold voltage of the switch transistors. As a result, when the threshold voltages of the switch transistors vary according to a manufacturing process, the voltage level of the control signal varies with the variation of the threshold voltages so as to turn on only one switch transistor during a sensing operation, thereby performing a more stable sensing operation.

摘要翻译： 一种具有更稳定的输入/输出（I / O）线路感测控制方案而不管阈值电压的变化及其感测控制方法的半导体存储器件。 半导体存储器件包括控制电路，其控制连接在一对I / O线和一对数据线之间的一对开关晶体管。 控制电路可以产生控制信号，该控制信号在断开另一个开关晶体管时导通一个开关晶体管，并根据开关晶体管的阈值电压的变化来改变控制信号的电压电平。 结果，当开关晶体管的阈值电压根据制造过程而变化时，控制信号的电压电平随着阈值电压的变化而变化，以便在感测操作期间仅导通一个开关晶体管，从而执行 更稳定的感测操作。

公开(公告)号：US08455940B2

公开(公告)日：2013-06-04

申请号：US13100488

申请日：2011-05-04

申请人： Jae-goo Lee ,  Young-woo Park ,  Byung-kwan You ,  Dong-sik Lee ,  Sang-yong Park

发明人： Jae-goo Lee ,  Young-woo Park ,  Byung-kwan You ,  Dong-sik Lee ,  Sang-yong Park

IPC分类号： H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/66477 ,  H01L29/7926

摘要： A nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer disposed between the channel layer and the gate conductive layer, and a first insulating layer spaced apart from the channel layer and disposed on the top and bottom of the gate conductive layer. The gate insulating layer extends between the gate conductive layer and the first insulating layer.

摘要翻译： 非易失性存储器件包括衬底，从衬底突出的沟道层，围绕沟道层的栅极导电层，设置在沟道层和栅极导电层之间的栅极绝缘层以及与沟道间隔开的第一绝缘层 并设置在栅极导电层的顶部和底部。 栅极绝缘层在栅极导电层和第一绝缘层之间延伸。