公开(公告)号：US20070026613A1

公开(公告)日：2007-02-01

申请号：US11503126

申请日：2006-08-14

Applicant: Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

Inventor： Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

IPC: H01L21/336

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Abstract translation: 具有能够防止有源区域和浮栅电极不对准的分离栅极的闪存器件及其制造方法包括在半导体衬底上依次层叠栅极氧化物层和浮置栅极导电层，形成 在形成有浮栅导电层的半导体衬底的预定区域中形成隔离层，并限定有源区。 然后，通过在活性区域上氧化浮栅导电层的预定部分来形成局部氧化层。 通过使用局部氧化物层图案化浮栅导电层来形成浮栅电极结构。

公开(公告)号：US20060001077A1

公开(公告)日：2006-01-05

申请号：US11152779

申请日：2005-06-15

Applicant: Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

Inventor： Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

IPC: H01L29/788 ,  H01L21/8238

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

Abstract: In a split gate type flash memory device, and a method of manufacturing the same, the device includes a memory cell array having a memory cell uniquely determined by a contact of a corresponding bit line and a corresponding word line, a floating gate formed on a semiconductor substrate to constitute the memory cell, the floating gate having a horizontal surface parallel to a main surface of the substrate, a vertical surface perpendicular to the main surface of the substrate, and a curved surface extending between the horizontal and vertical surfaces, a control gate formed over the curved surface of the floating gate in an area defined by an angle range of less than 90° between an extension line of the horizontal surface and an extension line of the vertical surface, and source and drain regions formed in an active region of the substrate.

Abstract translation: 在分闸式闪存器件及其制造方法中，该器件包括存储单元阵列，该存储单元阵列具有由对应的位线和对应的字线的接触唯一地确定的存储单元，形成在 半导体衬底以构成存储单元，浮置栅极具有平行于衬底的主表面的水平表面，垂直于衬底主表面的垂直表面以及在水平和垂直表面之间延伸的曲面，控制器 在浮动栅极的弯曲表面上形成的水平表面的延伸线和垂直表面的延伸线之间的角度范围小于90°的区域，以及形成在有源区域中的源极和漏极区域 的基底。

公开(公告)号：US20070170490A1

公开(公告)日：2007-07-26

申请号：US11624464

申请日：2007-01-18

Applicant: Jung-ho Moon ,  Chul-soon Kwon ,  Jae-min Yu ,  Jae-hyun Park ,  Young-cheon Jeong ,  In-gu Yoon

Inventor： Jung-ho Moon ,  Chul-soon Kwon ,  Jae-min Yu ,  Jae-hyun Park ,  Young-cheon Jeong ,  In-gu Yoon

IPC: H01L29/788 ,  H01L21/8238

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7885

Abstract: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on hte semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be elecrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.

Abstract translation: 非易失性存储器件包括半导体衬底; 源区域，其形成在所述半导体衬底中; 形成为与半导体衬底上的源极区域重叠的栅极绝缘膜; 形成在所述栅极绝缘膜上的浮栅，以具有在与所述源极区重叠的部分中形成均匀电场的结构; 形成为从浮置栅极的上部的浮动栅极的一个侧壁电隔离的控制栅极，插入在浮置栅极和控制栅极之间的栅极间绝缘膜，以及漏极区域 其形成为与控制栅极的另一侧相邻。

公开(公告)号：US20050250282A1

公开(公告)日：2005-11-10

申请号：US11119801

申请日：2005-05-03

Applicant: Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

Inventor： Eui-youl Ryu ,  Chul-soon Kwon ,  Jin-woo Kim ,  Yong-hee Kim ,  Dai-geun Kim ,  Joo-chan Kim

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.

Abstract translation: 具有能够防止有源区域和浮栅电极不对准的分离栅极的闪存器件及其制造方法包括在半导体衬底上依次层叠栅极氧化物层和浮置栅极导电层，形成 在形成有浮栅导电层的半导体衬底的预定区域中形成隔离层，并限定有源区。 然后，通过在活性区域上氧化浮栅导电层的预定部分来形成局部氧化层。 通过使用局部氧化物层图案化浮栅导电层来形成浮栅电极结构。

公开(公告)号：US20050112821A1

公开(公告)日：2005-05-26

申请号：US10982784

申请日：2004-11-08

Applicant: Yong-hee Kim ,  Chul-soon Kwon ,  Jin-woo Kim ,  Joo-chan Kim ,  Dae-geun Kim ,  Eui-youl Ryu

Inventor： Yong-hee Kim ,  Chul-soon Kwon ,  Jin-woo Kim ,  Joo-chan Kim ,  Dae-geun Kim ,  Eui-youl Ryu

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11536 ,  H01L29/66553 ,  H01L29/66825

Abstract: A method of manufacturing split-gate memory provides a control gate insulating film and the tunneling insulating film in a cell region, a high voltage gate insulating film in a high voltage region, and a low voltage gate insulating film in a low voltage region, all having different thickness. Additionally, a pre-cleaning process removes an outer sidewall portion of a spacer to form a tip portion of a floating gate that overlaps a control gate line formed proximate the floating gate.

Abstract translation: 制造分离栅极存储器的方法在单元区域中提供控制栅极绝缘膜和隧道绝缘膜，在高压区域中提供高电压栅极绝缘膜，以及在低电压区域中提供低电压栅极绝缘膜，全部 具有不同的厚度。 此外，预清洁处理除去间隔物的外侧壁部分以形成与形成在浮动栅极附近形成的控制栅极线重叠的浮栅的尖端部分。

公开(公告)号：US20110207265A1

公开(公告)日：2011-08-25

申请号：US13064960

申请日：2011-04-28

Applicant: Yong-wook Kwon ,  Chul-soon Kwon ,  Young-cheon Jeong

Inventor： Yong-wook Kwon ,  Chul-soon Kwon ,  Young-cheon Jeong

IPC: H01L21/50

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C2213/79

Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.

公开(公告)号：US07956343B2

公开(公告)日：2011-06-07

申请号：US12010921

申请日：2008-01-31

Applicant: Yong-wook Kwon ,  Chul-soon Kwon ,  Young-cheon Jeong

Inventor： Yong-wook Kwon ,  Chul-soon Kwon ,  Young-cheon Jeong

IPC: H01L47/00

CPC classification number: H01L27/24 ,  G11C13/0004 ,  G11C2213/79

Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.

Abstract translation: 示例性实施例提供了使用电阻元件的非易失性存储器件。 非易失性存储器件可以包括半导体衬底，半导体衬底上的多个可变电阻图案以及与可变电阻图案相平行并耦合到接地电压的多个散热器图案。

公开(公告)号：US07553726B2

公开(公告)日：2009-06-30

申请号：US11505355

申请日：2006-08-17

Applicant: In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

Inventor： In-gu Yoon ,  Chul-soon Kwon ,  Jae-won Um ,  Jung-ho Moon

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.

Abstract translation: 制造非易失性存储器件的方法可以包括在半导体衬底上形成分离的浮置栅极，在半导体衬底上形成控制栅极，在半导体衬底的表面上保形地形成缓冲膜，将离子注入半导体衬底 浮置栅极，形成与各对浮置栅极的每个浮置栅极部分重叠的共同源极区域，在缓冲膜上沉积绝缘膜，在浮置栅极和控制栅极的侧壁处蚀刻缓冲膜和绝缘膜 在浮置栅极和控制栅极的侧壁处形成间隔物，并且在除了形成公共源极区域的控制栅极的一侧之外的控制栅极的一侧的半导体衬底中形成漏极区域。

公开(公告)号：US06977200B2

公开(公告)日：2005-12-20

申请号：US10982784

申请日：2004-11-08

Applicant: Yong-hee Kim ,  Chul-soon Kwon ,  Jin-woo Kim ,  Joo-chan Kim ,  Dae-geun Kim ,  Eui-youl Ryu

Inventor： Yong-hee Kim ,  Chul-soon Kwon ,  Jin-woo Kim ,  Joo-chan Kim ,  Dae-geun Kim ,  Eui-youl Ryu

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11536 ,  H01L29/66553 ,  H01L29/66825

Abstract: A method of manufacturing split-gate memory provides a control gate insulating film and the tunneling insulating film in a cell region, a high voltage gate insulating film in a high voltage region, and a low voltage gate insulating film in a low voltage region, all having different thickness. Additionally, a pre-cleaning process removes an outer sidewall portion of a spacer to form a tip portion of a floating gate that overlaps a control gate line formed proximate the floating gate.

公开(公告)号：US5899740A

公开(公告)日：1999-05-04

申请号：US923279

申请日：1997-09-04

Applicant: Chul-soon Kwon

Inventor： Chul-soon Kwon

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76859 ,  H01L21/76843 ,  H01L21/7685 ,  H01L23/53238 ,  H01L2924/0002

Abstract: Interconnects for integrated circuit substrates are formed by forming a diffusion-barrier film on an integrated circuit substrate and amorphizing the diffusion-barrier film to create an amorphous diffusion-barrier film. A copper film is then formed on the amorphous diffusion-barrier film. Amorphizing may be performed by implanting ions into the diffusion-barrier film. The diffusion-barrier film can include Mo, W, Ti, Wn, TiW, TiN and the ions may be boron, nitrogen and silicon ions. Interconnect structures according to the invention include an amorphous conductive diffusion-barrier film on an integrated circuit substrate and a copper film on the amorphous conductive diffusion-barrier film. The amorphous conductive diffusion-barrier film preferably contains ions therein. The amorphous conductive diffusion-barrier film and the ions may be selected from materials as described above.

Abstract translation: 用于集成电路基板的互连通过在集成电路基板上形成扩散阻挡膜并使该扩散阻挡膜非晶化以形成无定形扩散阻挡膜而形成。 然后在无定形扩散阻挡膜上形成铜膜。 可以通过将离子注入到扩散阻挡膜中来进行非晶化。 扩散阻挡膜可以包括Mo，W，Ti，Wn，TiW，TiN，离子可以是硼，氮和硅离子。 根据本发明的互连结构包括集成电路基板上的非晶导电扩散阻挡膜和非晶导电扩散阻挡膜上的铜膜。 非晶导电性扩散阻挡膜优选在其中含有离子。 非晶导电扩散阻挡膜和离子可以选自如上所述的材料。