公开(公告)号：US20130013756A1

公开(公告)日：2013-01-10

申请号：US13462831

申请日：2012-05-03

Applicant: Chun-Nan Lin ,  Chin-Yi Lin ,  Chih-Hsiang Ho ,  Chien-Tao Wang

Inventor： Chun-Nan Lin ,  Chin-Yi Lin ,  Chih-Hsiang Ho ,  Chien-Tao Wang

IPC: G06F15/177

CPC classification number: G06F11/2005

Abstract: The present invention provides a network unit replacing method for an embedded system device having an internal network unit and a related embedded system device. The network unit replacing method comprises: detecting a network unit type of the embedded system device, to generate a detecting result; and when the detecting result indicates that the embedded system device has at least an external network unit currently, initializing the external network unit to make the embedded system device access network via the external network unit instead of the internal network unit.

Abstract translation: 本发明提供一种具有内部网络单元和相关嵌入式系统设备的嵌入式系统设备的网络单元替换方法。 网络单元替换方法包括：检测嵌入式系统设备的网络单元类型，以产生检测结果; 并且当检测结果表示嵌入式系统设备至少具有外部网络单元时，初始化外部网络单元以使嵌入式系统设备经由外部网络单元而不是内部网络单元接入网络。

公开(公告)号：US20120270392A1

公开(公告)日：2012-10-25

申请号：US13537054

申请日：2012-06-29

Applicant: Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

Inventor： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

IPC: H01L21/768

CPC classification number: C23C14/165 ,  C23C14/3492 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

Abstract: A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

Abstract translation: 提供了一种有源器件阵列衬底的制造方法。 有源器件阵列衬底具有至少一个图案化导电层。 图案化导电层包括铜层。 铜层的与铜层的法线平行的截面包括层叠在第一梯形上的第一梯形和第二梯形。 第一梯形的底角和第二梯形的底角是锐角，第一梯形的底角与第二梯形的底角之间的差为约5°至约30°。

公开(公告)号：US20100038645A1

公开(公告)日：2010-02-18

申请号：US12582964

申请日：2009-10-21

Applicant: Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

Inventor： Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

IPC: H01L33/00

CPC classification number: H01L29/458 ,  H01L27/124 ,  H01L29/41733

Abstract: A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

Abstract translation: 提供了一种显示元件及其制造方法。 该方法包括以下步骤：在衬底上形成具有栅极的第一图案化导电层和其上的电介质层; 在所述电介质层上形成图案化的半导体层，其中所述图案化半导体层具有沟道区，源极和漏极，并且其中所述源极和漏极位于所述沟道区的相对侧上; 选择性地沉积仅包裹图案化半导体层的阻挡层; 在阻挡层上和源极和漏极之上形成第二图案化导电层。 在通过该方法制造的显示元件中，阻挡层仅包裹图案化的半导体层。

公开(公告)号：US20080016268A1

公开(公告)日：2008-01-17

申请号：US11772237

申请日：2007-07-01

Applicant: Yung-Chun Lei ,  Chun-Nan Lin

Inventor： Yung-Chun Lei ,  Chun-Nan Lin

IPC: G06F12/00

CPC classification number: G06F8/65

Abstract: A processing system coupled to an apparatus is provided. The processing system includes: a non-volatile memory (NVM) storing firmware needed by the processing system; and an NVM control interface writing and reading data stored in the NVM. The apparatus verifies a previous piece of data being already written into the NVM, and the NVM control interface writes a current piece of data into the NVM.

Abstract translation: 提供耦合到装置的处理系统。 处理系统包括：存储由处理系统所需的固件的非易失性存储器（NVM）; 以及一个NVM控制接口，写入和读取存储在NVM中的数据。 该装置验证先前已经写入NVM的数据，NVM控制接口将当前数据写入NVM。

公开(公告)号：US20070052008A1

公开(公告)日：2007-03-08

申请号：US11272683

申请日：2005-11-15

Applicant: Chih-Ping Chung ,  Chun-Nan Lin ,  Chung-Yi Chen ,  Hung-Kwei Liao

Inventor： Chih-Ping Chung ,  Chun-Nan Lin ,  Chung-Yi Chen ,  Hung-Kwei Liao

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.

Abstract translation: 描述包括多个存储器单元的存储器结构。 每个存储单元包括衬底，浅沟槽隔离，间隔物，隧道氧化物和浮动栅极。 衬底中的浅沟槽隔离用于限定有源区。 间隔物位于浅沟槽隔离物的侧壁处，并且高于浅沟槽隔离。 隧道氧化物在有源区上。 浮动栅极在隧道氧化物上。

公开(公告)号：US20060217219A1

公开(公告)日：2006-09-28

申请号：US11089002

申请日：2005-03-24

Applicant: Chun-Nan Lin

Inventor： Chun-Nan Lin

IPC: A63B41/00

CPC classification number: A63B41/10 ,  A63B45/00

Abstract: A ball with a foam carcass has an inner bladder, a winding layer, a foam carcass layer, a colored rubber ink layer, and a leather layer. The inner bladder is hollow. The winding layer is attached to and covers the inner bladder. The colored rubber ink is brushed on and covers the foam carcass layer. The foam carcass layer with the colored rubber ink layer with the colored rubber ink is attached to and covers the winding layer to form a foam covered carcass. The foam covered carcass is vulcanized. The colored rubber ink layer covers the uneven foam-carcass layer to form an even foam covered carcass. The leather layer is attached to the foam covered carcass.

公开(公告)号：US06795893B2

公开(公告)日：2004-09-21

申请号：US09748447

申请日：2000-12-22

Applicant: Wen-Yi Wu ,  Jyh-Shin Pan ,  Chun-Nan Lin

Inventor： Wen-Yi Wu ,  Jyh-Shin Pan ,  Chun-Nan Lin

IPC: G06F1200

CPC classification number: G06F3/0613 ,  G06F3/0656 ,  G06F3/0677 ,  G11B2020/1062

Abstract: In a recordable disk recording controller circuit, a data buffer manager receives a command and sends the command to a micro-controller. The micro-controller generates a set of register batches from each command and sends the register data and index of the register batch to a batch register controller. The batch register controller receives the register data and index of the register batch from the micro-controller and stores the received register data and index of the register batch in a batch buffer. The batch register controller retrieves the register batches from the batch buffer and writes the master registers of an encoder controller based on the register index and register data of the register batches after the master registers of the encoder controller are updated into the slave registers of the encoder controller. The encoder controller generates control signals to a recording circuit depending on updated slave registers. Such control signals cause the recording circuit to record a signal representative of signal data on a recordable disk located in a recordable disk driver.

Abstract translation: 在可记录盘记录控制器电路中，数据缓冲器管理器接收命令并将命令发送到微控制器。 微控制器从每个命令生成一组寄存器批，并将寄存器批次的寄存器数据和索引发送到批量寄存器控制器。 批处理寄存器控制器从微控制器接收寄存器数据的寄存器数据和索引，并将接收到的寄存器数据和寄存器批次的索引存储在批量缓冲器中。 批量寄存器控制器从批量缓冲器中检索寄存器批次，并在编码器控制器的主寄存器更新到编码器的从寄存器之后，基于寄存器索引和寄存器批次的寄存器数据写入编码器控制器的主寄存器 控制器。 编码器控制器根据更新的从机寄存器向记录电路生成控制信号。 这种控制信号使得记录电路将表示信号数据的信号记录在位于可记录磁盘驱动器中的可记录盘上。

公开(公告)号：US08729055B2

公开(公告)日：2014-05-20

申请号：US12782395

申请日：2010-05-18

Applicant: Chun-Nan Lin ,  Huang-Yao Tu ,  A-Mei Huang ,  Bai-Luh Wei ,  Kim-Hong Gan ,  Tzyh-Chyuan Hour ,  Shyh-Chyun Yang ,  Yeong-Shiau Pu ,  Shen-Jeu Won

Inventor： Chun-Nan Lin ,  Huang-Yao Tu ,  A-Mei Huang ,  Bai-Luh Wei ,  Kim-Hong Gan ,  Tzyh-Chyuan Hour ,  Shyh-Chyun Yang ,  Yeong-Shiau Pu ,  Shen-Jeu Won

IPC: A61K31/56 ,  A61K31/58 ,  A61K31/585

CPC classification number: A61K31/56 ,  A61K31/19 ,  A61K31/215 ,  A61K31/365 ,  A61K31/58 ,  A61K31/585 ,  C07C61/29 ,  C07C69/145 ,  C07C69/34 ,  C07C69/533 ,  C07C69/757 ,  C07D313/08

Abstract: Several ursolic acid derivatives and pharmaceutical compositions thereof are provided. The ursolic acid derivatives and the pharmaceutical compositions thereof have at least one of an anticancer and an anti-inflammatory effects. A method for increasing a reactive oxygen species in a cell is also provided. The method comprises a step of providing the cell with a pharmaceutical composition including an ursolic acid derivative.

Abstract translation: 提供了几种熊果酸衍生物及其药物组合物。 熊果酸衍生物及其药物组合物具有抗癌和抗炎作用中的至少一种。 还提供了增加电池中活性氧的方法。 该方法包括向细胞提供包含熊果酸衍生物的药物组合物的步骤。

公开(公告)号：US20130119371A1

公开(公告)日：2013-05-16

申请号：US13444860

申请日：2012-04-12

Applicant: Hao-Lin Chiu ,  Chi-Jui Lin ,  Shu-Wei Tsao ,  Chun-Nan Lin ,  Po-Liang Yeh ,  Shine-Kai Tseng

Inventor： Hao-Lin Chiu ,  Chi-Jui Lin ,  Shu-Wei Tsao ,  Chun-Nan Lin ,  Po-Liang Yeh ,  Shine-Kai Tseng

IPC: H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/42384 ,  H01L29/7869

Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.

Abstract translation: 提供了包括源极，漏极，氧化物半导体层，栅极和栅极绝缘体层的有源器件。 源极包括彼此平行的第一条纹电极和与其连接的第一连接电极。 漏极包括彼此平行的第二条状电极和与其连接的第二连接电极，其中第一条形电极和第二条状电极彼此平行，电隔离并交替布置，并且之间形成之字形沟槽。 门沿着之字形沟槽延伸。 氧化物半导体层与源极和漏极接触，其中氧化物半导体层和每个第一条带电极之间的接触面积基本上等于每个第一条带电极的布局面积，并且每个第二条带电极之间的接触面积基本上等于 每个第二条纹电极的布局区域。

公开(公告)号：US08329940B2

公开(公告)日：2012-12-11

申请号：US12649437

申请日：2009-12-30

Applicant: Chun-Nan Lin ,  Dravidum Maitraie ,  Jih-Pyang Wang ,  Chi-Feng Hung ,  Huang-Yao Tu ,  Ya-Ting Liou ,  Bai-Luh Wei ,  Shyh-Chyun Yang

Inventor： Chun-Nan Lin ,  Dravidum Maitraie ,  Jih-Pyang Wang ,  Chi-Feng Hung ,  Huang-Yao Tu ,  Ya-Ting Liou ,  Bai-Luh Wei ,  Shyh-Chyun Yang

IPC: C07C61/12 ,  C07C69/74 ,  C07D313/06

CPC classification number: C07D313/06 ,  A61K31/19 ,  A61K31/215 ,  A61K31/335 ,  C07C231/02 ,  C07C231/12 ,  C07D313/08 ,  C07J63/008 ,  C07J73/003

Abstract: The present invention provides a chemical compound having the structure being one selected from a group consisting of wherein R1 is one selected from a group consisting of COOCH3, COOCH2Ph, CONHCH(CH3)2 and CONHC6H5, R2 is one selected from a group consisting of H, CH3 and CH(CH3)2, R3 is one selected from a group consisting of H, CH3, CH(CH3)2 and CH2Ph, and R4 is one of CH(CH3)2 and C6H5.

Abstract translation: 本发明提供一种具有以下结构的化合物：其中R 1为选自COOCH 3，COOCH 2 Ph，CONHCH（CH 3）2和CONHC 6 H 5中的一个，R 2为选自H ，CH 3和CH（CH 3）2，R 3是选自H，CH 3，CH（CH 3）2和CH 2 Ph的一个，R 4是CH（CH 3）2和C 6 H 5之一。