公开(公告)号：US20120270392A1

公开(公告)日：2012-10-25

申请号：US13537054

申请日：2012-06-29

申请人： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

发明人： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

IPC分类号： H01L21/768

CPC分类号： C23C14/165 ,  C23C14/3492 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： A fabricating method of an active device array substrate is provided. The active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

摘要翻译： 提供了一种有源器件阵列衬底的制造方法。 有源器件阵列衬底具有至少一个图案化导电层。 图案化导电层包括铜层。 铜层的与铜层的法线平行的截面包括层叠在第一梯形上的第一梯形和第二梯形。 第一梯形的底角和第二梯形的底角是锐角，第一梯形的底角与第二梯形的底角之间的差为约5°至约30°。

公开(公告)号：US08270178B2

公开(公告)日：2012-09-18

申请号：US12822201

申请日：2010-06-24

申请人： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

发明人： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

IPC分类号： H05K7/00 ,  H01L27/14 ,  H01L23/48

CPC分类号： C23C14/165 ,  C23C14/3492 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

摘要翻译： 有源器件阵列衬底具有至少一个图案化导电层。 图案化导电层包括铜层。 铜层的与铜层的法线平行的截面包括层叠在第一梯形上的第一梯形和第二梯形。 第一梯形的底角和第二梯形的底角是锐角，第一梯形的底角与第二梯形的底角之间的差为约5°至约30°。

公开(公告)号：US20110228502A1

公开(公告)日：2011-09-22

申请号：US12822201

申请日：2010-06-24

申请人： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

发明人： Po-Lin Chen ,  Chih-Yuan Lin ,  Yu-Min Lin ,  Chun-Nan Lin

IPC分类号： H05K7/00 ,  B05D5/12 ,  C23C14/34 ,  H05K1/09

CPC分类号： C23C14/165 ,  C23C14/3492 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908

摘要： An active device array substrate has at least one patterned conductive layer. The patterned conductive layer includes a copper layer. A cross-section of the copper layer which is parallel to a normal line direction of the copper layer includes a first trapezoid and a second trapezoid stacked on the first trapezoid. A base angle of the first trapezoid and a base angle of the second trapezoid are acute angles, and a difference between the base angle of the first trapezoid and the base angle of the second trapezoid is from about 5° to about 30°.

摘要翻译： 有源器件阵列衬底具有至少一个图案化导电层。 图案化导电层包括铜层。 铜层的与铜层的法线平行的截面包括层叠在第一梯形上的第一梯形和第二梯形。 第一梯形的底角和第二梯形的底角是锐角，第一梯形的底角与第二梯形的底角之间的差为约5°至约30°。

公开(公告)号：US20100038645A1

公开(公告)日：2010-02-18

申请号：US12582964

申请日：2009-10-21

申请人： Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

发明人： Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

IPC分类号： H01L33/00

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L29/41733

摘要： A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

摘要翻译： 提供了一种显示元件及其制造方法。 该方法包括以下步骤：在衬底上形成具有栅极的第一图案化导电层和其上的电介质层; 在所述电介质层上形成图案化的半导体层，其中所述图案化半导体层具有沟道区，源极和漏极，并且其中所述源极和漏极位于所述沟道区的相对侧上; 选择性地沉积仅包裹图案化半导体层的阻挡层; 在阻挡层上和源极和漏极之上形成第二图案化导电层。 在通过该方法制造的显示元件中，阻挡层仅包裹图案化的半导体层。

公开(公告)号：US07625788B2

公开(公告)日：2009-12-01

申请号：US12115855

申请日：2008-05-06

申请人： Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

发明人： Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L29/41733

摘要： A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

摘要翻译： 提供了一种显示元件及其制造方法。 该方法包括以下步骤：在衬底上形成具有栅极的第一图案化导电层和其上的电介质层; 在所述电介质层上形成图案化的半导体层，其中所述图案化半导体层具有沟道区，源极和漏极，并且其中所述源极和漏极位于所述沟道区的相对侧上; 选择性地沉积仅包裹图案化半导体层的阻挡层; 在阻挡层上和源极和漏极之上形成第二图案化导电层。 在通过该方法制造的显示元件中，阻挡层仅包裹图案化的半导体层。

公开(公告)号：US20090173944A1

公开(公告)日：2009-07-09

申请号：US12049362

申请日：2008-03-16

申请人： Po-Lin Chen ,  Ting Hsieh ,  Chun-Nan Lin ,  Wen-Ching Tsai

发明人： Po-Lin Chen ,  Ting Hsieh ,  Chun-Nan Lin ,  Wen-Ching Tsai

IPC分类号： H01L33/00 ,  H01L29/786

CPC分类号： H01L29/4908 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/78669

摘要： A thin film transistor (TFT) includes a substrate, a gate, a gate dielectric layer, a channel layer, a source and a drain. The gate and the gate dielectric layer are disposed on the substrate and the gate dielectric layer covers the gate. The channel layer is disposed on the gate dielectric layer over the gate, and the source and the drain are respectively disposed on a portion of the channel layer at both sides of the gate. At least one of the gate, the source and the drain has a lower conductive layer, an upper conductive layer and an intermediate conductive layer located between the lower conductive layer and the upper conductive layer. The material of the lower conductive layer is different from the material of the intermediate conductive layer, and the thickness of the lower conductive layer is less than or equal to about 150 Å.

摘要翻译： 薄膜晶体管（TFT）包括衬底，栅极，栅极电介质层，沟道层，源极和漏极。 栅极和栅极介电层设置在基板上，栅极电介质层覆盖栅极。 沟道层设置在栅极上的栅极介电层上，源极和漏极分别设置在栅极两侧的沟道层的一部分上。 栅极，源极和漏极中的至少一个具有位于下导电层和上导电层之间的下导电层，上导电层和中间导电层。 下导电层的材料与中间导电层的材料不同，下导电层的厚度小于或等于约150。

公开(公告)号：US20090153056A1

公开(公告)日：2009-06-18

申请号：US12060873

申请日：2008-04-02

申请人： Po-Lin Chen ,  Chun-Nan Lin ,  Shu-Feng Wu ,  Wen-Ching Tsai

发明人： Po-Lin Chen ,  Chun-Nan Lin ,  Shu-Feng Wu ,  Wen-Ching Tsai

IPC分类号： H01J7/44 ,  H01L21/04 ,  H01J9/00

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L27/1255

摘要： A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

摘要翻译： 提供了一种设置在包括薄膜晶体管（TFT），底部电容器电极，电介质层，上部电容器电极，钝化层和像素电极的基板上的像素结构。 具有源极/漏极和底部电容器电极的TFT设置在衬底上。 电介质层设置在底部电容器电极上。 上部电容器电极具有半导体层，阻挡层和金属层。 半导体层设置在底部电容器电极上方的电介质层上。 阻挡层设置在半导体层上。 其材料包括铜，铜合金或其组合的金属层设置在阻挡层上。 钝化层覆盖TFT和上电容器电极，并且具有暴露源极/漏极的第一开口。 像素电极通过第一开口与TFT电连接。

公开(公告)号：US08212256B2

公开(公告)日：2012-07-03

申请号：US12060873

申请日：2008-04-02

申请人： Po-Lin Chen ,  Chun-Nan Lin ,  Shu-Feng Wu ,  Wen-Ching Tsai

发明人： Po-Lin Chen ,  Chun-Nan Lin ,  Shu-Feng Wu ,  Wen-Ching Tsai

IPC分类号： H01L29/04

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L27/1255

摘要： A pixel structure disposed on a substrate including a thin film transistor (TFT), a bottom capacitor electrode, a dielectric layer, an upper capacitor electrode, a passivation layer, and a pixel electrode is provided. The TFT having a source/drain and the bottom capacitor electrode are disposed on the substrate. The dielectric layer is disposed on the bottom capacitor electrode. The upper capacitor electrode has a semiconductor layer, a barrier layer, and a metal layer. The semiconductor layer is disposed on the dielectric layer above the bottom capacitor electrode. The barrier layer is disposed on the semiconductor layer. The metal layer whose material includes copper, a copper alloy, or a combination thereof is disposed on the barrier layer. The passivation layer covers the TFT and the upper capacitor electrode and has a first opening exposing the source/drain. The pixel electrode is electrically connected to the TFT through the first opening.

摘要翻译： 提供了一种设置在包括薄膜晶体管（TFT），底部电容器电极，电介质层，上部电容器电极，钝化层和像素电极的基板上的像素结构。 具有源极/漏极和底部电容器电极的TFT设置在衬底上。 电介质层设置在底部电容器电极上。 上部电容器电极具有半导体层，阻挡层和金属层。 半导体层设置在底部电容器电极上方的电介质层上。 阻挡层设置在半导体层上。 其材料包括铜，铜合金或其组合的金属层设置在阻挡层上。 钝化层覆盖TFT和上电容器电极，并且具有暴露源极/漏极的第一开口。 像素电极通过第一开口与TFT电连接。

公开(公告)号：US07875885B2

公开(公告)日：2011-01-25

申请号：US12582964

申请日：2009-10-21

申请人： Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

发明人： Po-Lin Chen ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Kuo-Yuan Tu

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/00 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/458 ,  H01L27/124 ,  H01L29/41733

摘要： A display element and a method of manufacturing the same are provided. The method comprises the following steps: forming a first patterned conducting layer with a gate on a substrate and a dielectric layer thereon; forming a patterned semiconductor layer on the dielectric layer, wherein the patterned semiconductor layer has a channel region, a source and a drain, and wherein the source and the drain lie on the opposite sides of the channel region; selectively depositing a barrier layer, which only wraps the patterned semiconductor layer; forming a second patterned conducting layer on the barrier layer and above the source and the drain. In the display element manufactured by the method, the barrier layer only wraps the patterned semiconductor layer.

摘要翻译： 提供了一种显示元件及其制造方法。 该方法包括以下步骤：在衬底上形成具有栅极的第一图案化导电层和其上的电介质层; 在所述电介质层上形成图案化的半导体层，其中所述图案化半导体层具有沟道区，源极和漏极，并且其中所述源极和漏极位于所述沟道区的相对侧上; 选择性地沉积仅包裹图案化半导体层的阻挡层; 在阻挡层上和源极和漏极之上形成第二图案化导电层。 在通过该方法制造的显示元件中，阻挡层仅包裹图案化的半导体层。

公开(公告)号：US20090101903A1

公开(公告)日：2009-04-23

申请号：US12221615

申请日：2008-08-05

申请人： Po-Lin Chen ,  Kuo-Yuan Tu ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Shu-Feng Wu

发明人： Po-Lin Chen ,  Kuo-Yuan Tu ,  Wen-Ching Tsai ,  Chun-Nan Lin ,  Shu-Feng Wu

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L29/458 ,  H01L27/124

摘要： A thin-film transistor (TFT) includes a gate electrode, a gate dielectric layer, a semiconductor layer, source/drain electrodes, a passivation layer and a protection layer. The gate electrode is disposed on a substrate. The gate dielectric layer covers the gate electrode and the substrate. The semiconductor layer is disposed on the gate dielectric layer and above the gate electrode. The semiconductor layer has a channel region disposed above the gate electrode and source/drain regions disposed at both sides of the channel region. The source/drain electrodes are disposed on the source/drain regions of the semiconductor layer and each has a barrier layer disposed on the source/drain regions of the semiconductor layer and a conductive layer disposed on the barrier layer. The passivation layer is disposed over the surface of the source/drain electrodes. The protection layer is disposed over the substrate, the passivation layer, and the channel region of the semiconductor layer.

摘要翻译： 薄膜晶体管（TFT）包括栅电极，栅极电介质层，半导体层，源极/漏极，钝化层和保护层。 栅电极设置在基板上。 栅介质层覆盖栅电极和衬底。 半导体层设置在栅极电介质层上并在栅电极上方。 半导体层具有设置在沟道区两侧的栅电极和源极/漏极区上方的沟道区。 源极/漏极设置在半导体层的源极/漏极区域上，并且每个具有设置在半导体层的源极/漏极区域上的势垒层和设置在阻挡层上的导电层。 钝化层设置在源/漏电极的表面上。 保护层设置在衬底，钝化层和半导体层的沟道区之上。