公开(公告)号：US20080076215A1

公开(公告)日：2008-03-27

申请号：US11527616

申请日：2006-09-27

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

摘要翻译： 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

公开(公告)号：US07632729B2

公开(公告)日：2009-12-15

申请号：US11527616

申请日：2006-09-27

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

摘要翻译： 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

公开(公告)号：US07157351B2

公开(公告)日：2007-01-02

申请号：US10850747

申请日：2004-05-20

申请人： Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

发明人： Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

IPC分类号： H01L21/76

CPC分类号： H01L21/02057 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02307 ,  H01L21/31662 ,  H01L21/76224

摘要： A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

摘要翻译： 一种在表面特别是硅表面上清洗和形成氧化膜的方法。 表面最初被清洁，然后暴露于臭氧蒸汽，这在表面上形成氧化膜。 该方法在STI（浅沟槽隔离）结构的制造中在沟槽表面上形成预衬垫氧化膜特别有用。

公开(公告)号：US20050260827A1

公开(公告)日：2005-11-24

申请号：US10850747

申请日：2004-05-20

申请人： Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

发明人： Chung-Long Cheng ,  Kong-Beng Thei ,  Jung-Hui Kao

IPC分类号： H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/469 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/02057 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02307 ,  H01L21/31662 ,  H01L21/76224

摘要： A method for cleaning and forming an oxide film on a surface, particularly a silicon surface. The surface is initially cleaned and then exposed to ozone vapor, which forms the oxide film on the surface. The method is particularly useful for forming a pre-liner oxide film on trench surfaces in the fabrication of STI (shallow trench isolation) structures.

摘要翻译： 一种在表面特别是硅表面上清洗和形成氧化膜的方法。 表面最初被清洁，然后暴露于臭氧蒸汽，这在表面上形成氧化膜。 该方法在STI（浅沟槽隔离）结构的制造中在沟槽表面上形成预衬垫氧化膜特别有用。

公开(公告)号：US07803674B2

公开(公告)日：2010-09-28

申请号：US12468131

申请日：2009-05-19

申请人： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

发明人： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

摘要翻译： 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

公开(公告)号：US20100052058A1

公开(公告)日：2010-03-04

申请号：US12401876

申请日：2009-03-11

申请人： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/66545 ,  Y10S438/926

摘要： A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.

摘要翻译： 公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。 该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

公开(公告)号：US07298011B2

公开(公告)日：2007-11-20

申请号：US11215103

申请日：2005-08-30

申请人： Kong-Beng Thei ,  Chung-Long Cheng ,  Harry Chuang

发明人： Kong-Beng Thei ,  Chung-Long Cheng ,  Harry Chuang

IPC分类号： H01L29/94

CPC分类号： H01L29/6656 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/66507 ,  H01L29/6653

摘要： A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.

摘要翻译： 具有凹入的L形间隔物的半导体器件及其制造方法。 凹进的L形间隔件包括垂直部分和水平部分。 垂直部分设置在导体图案的下侧壁上，露出其上侧壁。 顶部间隔物在L形间隔件上，其中L形间隔件的垂直部分与顶部间隔物的宽度比为至少约2:1。

公开(公告)号：US20090298243A1

公开(公告)日：2009-12-03

申请号：US12468131

申请日：2009-05-19

申请人： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

发明人： Chung-Long Cheng ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Tzung-Chi Lee ,  Harry Chuang

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/4238 ,  H01L29/78636

摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

摘要翻译： 提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。 在衬底上形成第一绝缘层。 在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。 在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。 在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。 第一电介质层形成在每个半导体岛的一部分上。 导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。 一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

公开(公告)号：US20060163734A1

公开(公告)日：2006-07-27

申请号：US11041585

申请日：2005-01-24

申请人： Kong-Beng Thei ,  Chung-Long Cheng ,  Chung-Shi Liu ,  Harry Chuang

发明人： Kong-Beng Thei ,  Chung-Long Cheng ,  Chung-Shi Liu ,  Harry Chuang

IPC分类号： H01L23/48

CPC分类号： H01L23/5258 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a fuse structure and a method for manufacturing the fuse structure. In one example, the method includes providing a multilayer interconnect structure (MLI) over a semiconductor substrate. The MLI includes multiple fuse connection and bonding connection features. A passivation layer is formed over the MLI and patterned to form openings, with each opening being aligned with one of the fuse connection or bonding connection features. A conductive layer is formed on the passivation layer and in the openings. The conductive layer is patterned to form bonding features and fuse structures. Each bonding feature is in contact with one of the bonding connection features, and each fuse structure is in contact with two of the fuse connection features. A cap dielectric layer is formed over the fuse structures and patterned to expose at least one of the bonding features while leaving the fuse structures covered.

摘要翻译： 提供了一种熔丝结构和用于制造熔丝结构的方法。 在一个示例中，该方法包括在半导体衬底上提供多层互连结构（MLI）。 MLI包括多个保险丝连接和接合连接功能。 钝化层形成在MLI上方并被图案化以形成开口，其中每个开口与保险丝连接或接合连接特征中的一个对准。 在钝化层和开口中形成导电层。 将导电层图案化以形成结合特征和熔丝结构。 每个接合特征与接合连接特征之一接触，并且每个熔断器结构与两个熔断器连接特征接触。 在熔丝结构之上形成盖电介质层，并将其图案化以暴露粘合特征中的至少一个，同时保留熔丝结构。

公开(公告)号：US08153498B2

公开(公告)日：2012-04-10

申请号：US12401876

申请日：2009-03-11

申请人： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/8232

CPC分类号： H01L27/0629 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/66545 ,  Y10S438/926

摘要： A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.

摘要翻译： 公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。 该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。