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    LOGIC-KEEPING APPARATUS FOR IMPROVING SYSTEM-LEVEL ELECTROSTATIC DISCHARGE ROBUSTNESS
    1.
    发明申请
    LOGIC-KEEPING APPARATUS FOR IMPROVING SYSTEM-LEVEL ELECTROSTATIC DISCHARGE ROBUSTNESS 审中-公开
    改善系统级静电放电稳定性的LOGIC保持装置

    公开(公告)号：US20070252615A1

    公开(公告)日：2007-11-01

    申请号：US11309104

    申请日：2006-06-23

    申请人： Chyh-Yih Chang ,  Ching-Hua Huang

    发明人： Chyh-Yih Chang ,  Ching-Hua Huang

    IPC分类号： H03K19/003

    CPC分类号： H01L27/0266

    摘要： A logic-keeping apparatus including a logic judgment unit and a noise-event detection unit is disclosed. When the level at the input terminal of the logic judgment unit is larger than a first level, the output terminal thereof outputs a first logic state; when the level at the input terminal is smaller than a second level, the output terminal thereof outputs a second logic state; when the level at the input terminal is between the first level and the second level, the output terminal thereof keeps the previous logic state. The noise-event detection unit is for detecting whether a noise-event occurs (for example, an ESD event). Wherein, when a noise-even occurs in the system, the noise-event detection unit keeps the level at the input terminal of the logic judgment unit between the first level and the second level.

    摘要翻译： 公开了包括逻辑判断单元和噪声事件检测单元的逻辑保持装置。 当逻辑判断单元的输入端的电平大于第一电平时，其输出端输出第一逻辑状态; 当输入端的电平小于第二电平时，其输出端输出第二逻辑状态; 当输入端子的电平处于第一电平和第二电平之间时，其输出端保持先前的逻辑状态。 噪声事件检测单元用于检测是否发生噪声事件（例如，ESD事件）。 其中，当在系统中发生噪声均匀时，噪声事件检测单元将逻辑判断单元的输入端子处的电平保持在第一电平和第二电平之间。

    LOGIC-LATCHING APPARATUS FOR IMPROVING SYSTEM-LEVEL ELECTROSTATIC DISCHARGE ROBUSTNESS
    2.
    发明申请
    LOGIC-LATCHING APPARATUS FOR IMPROVING SYSTEM-LEVEL ELECTROSTATIC DISCHARGE ROBUSTNESS 审中-公开
    用于改进系统级静电放电稳定性的逻辑锁定装置

    公开(公告)号：US20070247183A1

    公开(公告)日：2007-10-25

    申请号：US11308823

    申请日：2006-05-11

    申请人： Chyh-Yih Chang ,  Ching-Hua Huang

    发明人： Chyh-Yih Chang ,  Ching-Hua Huang

    IPC分类号： H03K19/003

    CPC分类号： H03K19/007 ,  H03K19/00384 ,  H03K19/094

    摘要： A logic-latching apparatus includes a noise-event detection unit, a combinational logic unit and a latch unit. The noise-event detection unit is used for detecting whether or not a noise-event occurs (for example, an ESD). The latch unit is coupled with the noise-event detection unit and the combinational logic unit for latching the state of the combinational logic unit. When the output of the noise-event detection unit indicates that a noise-event occurs, the latch unit provides the input terminal of the combinational logic unit with a corresponding input signal according to the latched state of the combinational logic unit inside the latch unit to prevent the state of the combinational logic unit from being affected by the noise-event.

    摘要翻译： 逻辑锁定装置包括噪声事件检测单元，组合逻辑单元和锁存单元。 噪声事件检测单元用于检测是否发生噪声事件（例如，ESD）。 锁存单元与噪声事件检测单元和组合逻辑单元耦合，用于锁存组合逻辑单元的状态。 当噪声事件检测单元的输出指示发生噪声事件时，锁存单元根据闩锁单元内的组合逻辑单元的锁存状态向组合逻辑单元的输入端提供相应的输入信号， 防止组合逻辑单元的状态受到噪声事件的影响。

    Poly diode structure for photo diode
    4.
    发明授权
    Poly diode structure for photo diode 有权
    光二极管的聚二极管结构

    公开(公告)号：US07993956B2

    公开(公告)日：2011-08-09

    申请号：US11618685

    申请日：2006-12-29

    申请人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

    发明人： Yu-Da Shiu ,  Chyh-Yih Chang ,  Ming-Dou Ker ,  Che-Hao Chuang

    IPC分类号： H01L21/00

    CPC分类号： H01L31/103 ,  H01L27/14609 ,  H01L31/105

    摘要： An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

    摘要翻译： 用于将入射光信号转换成电信号的集成电路装置包括半导体衬底，形成在半导体衬底内部的阱区，形成在阱区上的电介质层和用于接收入射光信号的多晶硅层，形成 包括p型部分，n型部分和设置在p型和n型部分之间的未掺杂部分，其中阱区被偏置以控制多晶硅层以提供电信号 。

    Level shifter ESD protection circuit with power-on-sequence consideration
    5.
    发明授权
    Level shifter ESD protection circuit with power-on-sequence consideration 有权
    电平移位器ESD保护电路具有电源顺序考虑

    公开(公告)号：US07233468B2

    公开(公告)日：2007-06-19

    申请号：US11162652

    申请日：2005-09-19

    申请人： Chyh-Yih Chang ,  Kuo-Ching Chen

    发明人： Chyh-Yih Chang ,  Kuo-Ching Chen

    IPC分类号： H02H9/00

    CPC分类号： H02H9/046

    摘要： A level shifter ESD protection circuit with power-on-sequence consideration used for receiving a first signal and outputting a second signal is provided. The level shifter circuit includes an inverter, a first switch, a second switch, a voltage level shifting circuit, a first ESD clamp and a second ESD clamp circuits. When the first power supply has been powered on and the second power supply is off, the first and second switches will remain off resulting from the power-off of the second power supply. Therefore, the second power source would not be affected by the first power supply because of passing through the ESD protection circuit.

    摘要翻译： 提供了一种具有上电顺序考虑的电平移位器ESD保护电路，用于接收第一信号并输出​​第二信号。 电平移位器电路包括逆变器，第一开关，第二开关，电压电平移位电路，第一ESD钳位电路和第二ESD钳位电路。 当第一电源通电并且第二电源关闭时，由于第二电源的断电，第一和第二开关将保持关闭。 因此，由于通过ESD保护电路，第二电源不会受到第一电源的影响。

    ELECTROSTATIC DISCHARGE (ESD) PROTECTION APPARATUS FOR PROGRAMMABLE DEVICE
    6.
    发明申请
    ELECTROSTATIC DISCHARGE (ESD) PROTECTION APPARATUS FOR PROGRAMMABLE DEVICE 审中-公开
    用于可编程器件的静电放电（ESD）保护装置

    公开(公告)号：US20070053121A1

    公开(公告)日：2007-03-08

    申请号：US11308509

    申请日：2006-03-31

    申请人： Chyh-Yih Chang ,  Yan-Nan Li ,  Kun-Tai Wu

    发明人： Chyh-Yih Chang ,  Yan-Nan Li ,  Kun-Tai Wu

    IPC分类号： H02H9/00

    CPC分类号： H02H9/046

    摘要： An electronic static discharge (ESD) protection apparatus for a programmable device is provided. The apparatus can improve the turn-on efficiency and reduce the surface area of the chip efficiently by providing a low impedance current path which can sufficiently lower the voltage of the programmable device when ESD occurs. The ESD protection apparatus includes an ESD protection device, a programmable device, a first circuit, a second circuit, and a third circuit.

    摘要翻译： 提供了一种用于可编程器件的电子静电放电（ESD）保护装置。 该装置可以通过提供低阻抗电流路径来有效地提高开启效率并降低芯片的表面积，这可以在ESD发生时充分降低可编程器件的电压。 ESD保护装置包括ESD保护装置，可编程装置，第一电路，第二电路和第三电路。

    SEPARATED POWER ESD PROTECTION CIRCUIT AND INTEGRATED CIRCUIT THEREOF
    7.
    发明申请
    SEPARATED POWER ESD PROTECTION CIRCUIT AND INTEGRATED CIRCUIT THEREOF 失效
    分离电源ESD保护电路及其集成电路

    公开(公告)号：US20050286186A1

    公开(公告)日：2005-12-29

    申请号：US10711568

    申请日：2004-09-24

    申请人： Chyh-Yih Chang

    发明人： Chyh-Yih Chang

    IPC分类号： H01L27/04 ,  H01L23/60 ,  H01L27/02 ,  H02H9/00

    CPC分类号： H01L27/0251 ,  H01L27/0292

    摘要： A separated power ESD protection circuit is disclosed. The separated power ESD protection circuit is coupled between a first and a second power lines. The separated power ESD protection circuit has a first diode, a second diode and a MOS transistor. The first diode has an anode and a cathode, wherein the anode is coupled to the first power line. The source of the MOS transistor is coupled to the second power line. The anode of the second diode is coupled to the second power line and cathode is coupled to the first power line. The first diode and the MOS transistor form a parasitic silicon-controlled rectifier (SCR) so as to provide a discharge route for ESD.

    摘要翻译： 公开了一种分离的电源ESD保护电路。 分离式电力ESD保护电路耦合在第一和第二电力线之间。 分离式电源ESD保护电路具有第一二极管，第二二极管和MOS晶体管。 第一二极管具有阳极和阴极，其中阳极耦合到第一电力线。 MOS晶体管的源极耦合到第二电源线。 第二二极管的阳极耦合到第二电源线，阴极耦合到第一电力线。 第一二极管和MOS晶体管形成寄生硅控整流器（SCR），以提供用于ESD的放电路径。

    SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection
    8.
    发明授权
    SCR devices in silicon-on-insulator CMOS process for on-chip ESD protection 有权
    用于片上ESD保护的硅绝缘体CMOS工艺中的SCR器件

    公开(公告)号：US06750515B2

    公开(公告)日：2004-06-15

    申请号：US10062714

    申请日：2002-02-05

    申请人： Ming-Dou Ker ,  Kei-Kang Hung ,  Chyh-Yih Chang

    发明人： Ming-Dou Ker ,  Kei-Kang Hung ,  Chyh-Yih Chang

    IPC分类号： H01L2776

    CPC分类号： H01L27/0262 ,  H01L27/1203

    摘要： A silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer, and a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a silicon controlled rectifier to provide electrostatic discharge protection.

    摘要翻译： 硅隔离器CMOS集成电路器件包括半导体衬底，形成在半导体衬底上的隔离层，具有形成在隔离层上的栅极，漏极区域和源极区域的n型MOS晶体管，以及 p型MOS晶体管，其具有形成在隔离层上并与n型MOS晶体管邻接的栅极，漏极区域和源极区域，其中n型MOS晶体管和p型MOS晶体管形成硅控制 整流器提供静电放电保护。