公开(公告)号：US10116473B1

公开(公告)日：2018-10-30

申请号：US15926395

申请日：2018-03-20

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Pradeep Dhananjay ,  Tejasvi Das ,  Bhupendra Manola ,  Bruce E. Duewer

IPC: H04L25/49 ,  H04L25/03 ,  H04R3/04 ,  H04B14/04

CPC classification number: H04L25/4927 ,  H03F1/0227 ,  H03F1/025 ,  H03F3/187 ,  H03F3/213 ,  H03F2200/03 ,  H03F2200/331 ,  H04B14/046 ,  H04L25/03159 ,  H04R3/04

Abstract: An apparatus may include a delta-sigma modulator for quantization noise shaping of a digital signal, a digital-to-analog converter configured to generate an analog signal from the digital signal, and an amplifier configured to amplify the analog signal and powered from a charge pump, wherein the charge pump is configured to operate at a switching frequency approximately equal to a zero of a modulator noise transfer function of the delta-sigma modulator, such that the impact of charge pump noise on a total harmonic distortion noise of the apparatus is minimized.

公开(公告)号：US20220149864A1

公开(公告)日：2022-05-12

申请号：US17096582

申请日：2020-11-12

Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR, LTD.

Inventor： Chandra Prakash ,  Bhupendra Manola ,  John L. Melanson

IPC: H03M3/00

Abstract: An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source. Alternatively, or in combination, correction may be applied to the output of the active converters by digital adjustment of output values.

公开(公告)号：US11777517B2

公开(公告)日：2023-10-03

申请号：US17096582

申请日：2020-11-12

Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR, LTD.

Inventor： Chandra Prakash ,  Bhupendra Manola ,  John L. Melanson

IPC: H03M3/00

CPC classification number: H03M3/354 ,  H03M3/422

Abstract: An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source. Alternatively, or in combination, correction may be applied to the output of the active converters by digital adjustment of output values.

公开(公告)号：US10432150B2

公开(公告)日：2019-10-01

申请号：US15993955

申请日：2018-05-31

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Ramya Balasundaram ,  Bhupendra Manola ,  Pradeep Dhananjay

IPC: H03F1/30 ,  H03F3/45 ,  H03F3/187 ,  H03F1/52 ,  G06F3/16

Abstract: An apparatus may include a digital-to-analog converter configured to convert a digital audio input signal into a differential analog input signal with a substantially non-zero common-mode voltage, an amplifier configured to receive the differential analog input signal and generate at an amplifier output a ground-centered output signal from the differential analog input signal, a clamp configured to selectively couple and decouple the amplifier output to a ground voltage, and a controller configured to control the clamp to selectively couple and decouple the amplifier output to a ground voltage responsive to transitions between power states of a device comprising the apparatus and control the differential analog input signal generated by the digital-to-analog converter in order to minimize a level transition current through an output load coupled to the amplifier output during transitions between the power states.