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公开(公告)号：US20240039554A1
公开(公告)日：2024-02-01
申请号：US17876679
申请日：2022-07-29
Applicant: Cisco Technology, Inc.
Inventor： Bibhu Prasad Das , Romesh Kumar Nandwana , Richard Van Hoesen Booth , Pavan Kumar Hanumolu , Kadaba Lakshmikumar
IPC: H03M3/00
Abstract: An apparatus includes a delta-sigma modulator digital-to-analog converter section having a multiple stag cascaded error cancellation architecture, each stage including a delta-sigma modulator followed by a digital-to-analog converter, the delta-sigma modulator digital-to-analog converter section configured to receive a digital input and to generate an analog output. An inverting amplifier-based analog filter is coupled to receive the analog output, the inverting amplifier-based analog filter configured to filter the analog output to produce a filtered analog output.
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公开(公告)号：US11811375B2
公开(公告)日：2023-11-07
申请号：US17224497
申请日：2021-04-07
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Alexander Kurylak , Romesh Kumar Nandwana
CPC classification number: H03F3/45475 , H03G3/30 , H03F2200/129
Abstract: An asymmetric signal path approach is used to extract differential signals out of the photodetector (e.g., a photodiode) for amplification by a differential transimpedance amplifier (TIA). This asymmetric-path differential TIA configuration has less low-frequency Inter Symbol Interference (ISI) (also known as Baseline Wander), less high-frequency noise amplification, and higher bandwidth capabilities. There is no power penalty with this design in comparison to a single-ended TIA, can extend the range of the link for a given system power consumption, and can decrease transmitter power for a given range.
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3.发明授权公开(公告)号：US11671105B2
公开(公告)日：2023-06-06
申请号：US17720446
申请日：2022-04-14
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Romesh Kumar Nandwana , Kadaba Lakshmikumar , Pavan Kumar Hanumolu
CPC classification number: H03L7/099 , H03B5/124 , H03B5/1212 , H03B5/1228 , H03L7/085 , H03L7/093 , H03D5/00
Abstract: An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.
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公开(公告)号：US11901906B1
公开(公告)日：2024-02-13
申请号：US17887709
申请日：2022-08-15
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Romesh Kumar Nandwana , Pavan Kumar Hanumolu , Kadaba Lakshmikumar
CPC classification number: H03L7/099 , G04F10/005 , G06G7/60 , G06N3/063 , H03B7/08 , H03L7/091 , H04B1/16
Abstract: Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.
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公开(公告)号：US20230155618A1
公开(公告)日：2023-05-18
申请号：US17528413
申请日：2021-11-17
Applicant: Cisco Technology, Inc.
Inventor： Romesh Kumar Nandwana , Abhishek Bhat , Kadaba Lakshmikumar , Pavan Kumar Hanumolu
Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.
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Patent Agency Ranking
公开(公告)号：US20220329222A1
公开(公告)日：2022-10-13
申请号：US17224497
申请日：2021-04-07
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Alexander Kurylak , Romesh Kumar Nandwana
Abstract: An asymmetric signal path approach is used to extract differential signals out of the photodetector (e.g., a photodiode) for amplification by a differential transimpedance amplifier (TIA). This asymmetric-path differential TIA configuration has less low-frequency Inter Symbol Interference (ISI) (also known as Baseline Wander), less high-frequency noise amplification, and higher bandwidth capabilities. There is no power penalty with this design in comparison to a single-ended TIA, can extend the range of the link for a given system power consumption, and can decrease transmitter power for a given range.
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7.发明授权公开(公告)号：US11356107B1
公开(公告)日：2022-06-07
申请号：US17502512
申请日：2021-10-15
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Romesh Kumar Nandwana , Kadaba Lakshmikumar , Pavan Kumar Hanumolu
Abstract: An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.
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公开(公告)号：US12191915B1
公开(公告)日：2025-01-07
申请号：US17689634
申请日：2022-03-08
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Romesh Kumar Nandwana , Alexander C. Kurylak
Abstract: Techniques for implementing a differential differencing TIA for coherent applications are disclosed. A method includes receiving first and second optical signals from a 90 degree optical hybrid that receives a coherent optical signal, wherein the first and second optical signals each include one pair of sum and difference signals output by the 90 degree optical hybrid, generating, based on the first optical signal and from a first photo diode, a first differential signal, generating, based on the second optical signal and from a second photo diode, a second differential signal, differentially transconducting the first and second differential signals to produce first and second transconducted signals, performing a differencing operation on the first and second differential transconducted signals to produce a combined differential-differencing transconducted signal that is representative of the first optical signal and the second optical signal, and outputting the combined differential transconducted signal as a differential output.
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公开(公告)号：US12147201B2
公开(公告)日：2024-11-19
申请号：US17989045
申请日：2022-11-17
Applicant: Cisco Technology, Inc.
Inventor： Abhishek Bhat , Ajay Bharadwaj , Romesh Kumar Nandwana
Abstract: A multi-segment digital-to-time converter is provided. The digital-to-time converter includes a plurality of delay stages arranged in series, and a plurality of local synchronization logic circuits each configured to control an associated delay stage of the plurality of delay stages. Each local synchronization logic circuit provides a digital-to-time converter code and a reset signal to the associated delay stage synchronized to a local input clock and a local output clock of the associated delay stage.
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公开(公告)号：US11863222B2
公开(公告)日：2024-01-02
申请号：US17528413
申请日：2021-11-17
Applicant: Cisco Technology, Inc.
Inventor： Romesh Kumar Nandwana , Abhishek Bhat , Kadaba Lakshmikumar , Pavan Kumar Hanumolu
Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.
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