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公开(公告)号：US11863222B2
公开(公告)日：2024-01-02
申请号：US17528413
申请日：2021-11-17
摘要： A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.
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2.发明授权公开(公告)号：US11716087B1
公开(公告)日：2023-08-01
申请号：US17582466
申请日：2022-01-24
CPC分类号： H03L7/091 , H03L7/0992
摘要： Presented herein are techniques for implementing a differential sub-sampling phase locked loop (PLL). A method includes detecting a common-mode voltage on an output of a differential sub-sampling phase detector operating in the differential sub-sampling phase locked loop, and controlling, based on the common-mode voltage, a duty cycle of a feedback signal of the differential sub-sampling phase locked loop that is fed back to the differential sub-sampling phase detector.
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公开(公告)号：US11218113B1
公开(公告)日：2022-01-04
申请号：US17031462
申请日：2020-09-24
IPC分类号： H03B5/12
摘要： A voltage controlled oscillator (VCO) is described. The VCO includes a plurality of nodes coupled with a plurality of transistors, and a first inductor-capacitor (LC) tank coupled with a second LC tank. The first LC tank and the second LC tank include a shared inductor structure coupled to the plurality of nodes. The first LC tank and the second LC tank each include a capacitor. The capacitors are each coupled on a first side to a node of the plurality of nodes and on a second side to a respective capacitor in the other LC tank. The first LC tank and the second LC tank are configured to resonate at a fundamental frequency for differential-mode signals, and the first LC tank and the second LC tank are configured to resonate at twice the fundamental frequency for common-mode signals.
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公开(公告)号：US20240039554A1
公开(公告)日：2024-02-01
申请号：US17876679
申请日：2022-07-29
发明人： Bibhu Prasad Das , Romesh Kumar Nandwana , Richard Van Hoesen Booth , Pavan Kumar Hanumolu , Kadaba Lakshmikumar
IPC分类号： H03M3/00
摘要： An apparatus includes a delta-sigma modulator digital-to-analog converter section having a multiple stag cascaded error cancellation architecture, each stage including a delta-sigma modulator followed by a digital-to-analog converter, the delta-sigma modulator digital-to-analog converter section configured to receive a digital input and to generate an analog output. An inverting amplifier-based analog filter is coupled to receive the analog output, the inverting amplifier-based analog filter configured to filter the analog output to produce a filtered analog output.
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公开(公告)号：US11811375B2
公开(公告)日：2023-11-07
申请号：US17224497
申请日：2021-04-07
CPC分类号： H03F3/45475 , H03G3/30 , H03F2200/129
摘要： An asymmetric signal path approach is used to extract differential signals out of the photodetector (e.g., a photodiode) for amplification by a differential transimpedance amplifier (TIA). This asymmetric-path differential TIA configuration has less low-frequency Inter Symbol Interference (ISI) (also known as Baseline Wander), less high-frequency noise amplification, and higher bandwidth capabilities. There is no power penalty with this design in comparison to a single-ended TIA, can extend the range of the link for a given system power consumption, and can decrease transmitter power for a given range.
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6.发明授权公开(公告)号：US11671105B2
公开(公告)日：2023-06-06
申请号：US17720446
申请日：2022-04-14
CPC分类号： H03L7/099 , H03B5/124 , H03B5/1212 , H03B5/1228 , H03L7/085 , H03L7/093 , H03D5/00
摘要： An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.
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公开(公告)号：US11901906B1
公开(公告)日：2024-02-13
申请号：US17887709
申请日：2022-08-15
摘要： Presented herein are techniques for implementing a hybrid fractional-N sampling phase locked loop with accurate digital-to-time calibration. A method includes receiving, at a comparator, an output of a sampling phase detector of a phase locked loop, the output of the sampling phase detector of the phase locked loop also being supplied as a control source for a proportional control input of a voltage-controlled oscillator, supplying an output of the comparator as an input signal to a calibration loop of a digital-to-time converter, supplying an output of the digital-to-time converter to an input of the sampling phase detector, and supplying the output of the comparator as a control source for an integral control input of the voltage-controlled oscillator.
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公开(公告)号：US20230155618A1
公开(公告)日：2023-05-18
申请号：US17528413
申请日：2021-11-17
摘要： A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.
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公开(公告)号：US20220329222A1
公开(公告)日：2022-10-13
申请号：US17224497
申请日：2021-04-07
摘要： An asymmetric signal path approach is used to extract differential signals out of the photodetector (e.g., a photodiode) for amplification by a differential transimpedance amplifier (TIA). This asymmetric-path differential TIA configuration has less low-frequency Inter Symbol Interference (ISI) (also known as Baseline Wander), less high-frequency noise amplification, and higher bandwidth capabilities. There is no power penalty with this design in comparison to a single-ended TIA, can extend the range of the link for a given system power consumption, and can decrease transmitter power for a given range.
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10.发明授权公开(公告)号：US11356107B1
公开(公告)日：2022-06-07
申请号：US17502512
申请日：2021-10-15
摘要： An accurate replica oscillator-based frequency tracking loop (FTL) is provided. The replica oscillator used in the FTL can be at a lower frequency and therefore can consume much lower power compared to a main oscillator, such as an injection locked oscillator (ILO). The proposed FTL accurately sets the free running frequency of an ILO across process, voltage and temperature (PVT). Techniques are also provided to compensate the gain and offset error between the replica oscillator and the ILO.
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