公开(公告)号：US20220165907A1

公开(公告)日：2022-05-26

申请号：US17103792

申请日：2020-11-24

Applicant: Cisco Technology, Inc.

Inventor： Xunyuan ZHANG ,  Li LI ,  Prakash B. GOTHOSKAR ,  Soha NAMNABAT

IPC: H01L31/18 ,  H01L31/105 ,  H01L31/0368

Abstract: The embodiments of the present disclosure describe a stressed Ge PD and fabrications techniques for making the same. In one embodiment, a stressor material is deposited underneath an already formed Ge PD. To do so, wafer bonding can be used to bond the wafer containing the Ge PD to a second, handler wafer. Doing so provides support to remove the substrate of the wafer so that a stressor material (e.g., silicon nitride, diamond-like carbon, or silicon-germanium) can be disposed underneath the Ge PD. The stress material induces a stress or strain in the crystal lattice of the Ge which changes its bandgap and improves its responsivity.

公开(公告)号：US20250015213A1

公开(公告)日：2025-01-09

申请号：US18346558

申请日：2023-07-03

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar K. PATEL ,  Xunyuan ZHANG

IPC: H01L31/0352 ,  H01L31/0232 ,  H01L31/105 ,  H01L31/18

Abstract: The present disclosure relates to a photodiode and method of forming the photodiode. The photodiode includes a doped layer and an absorption region positioned on the doped layer. The absorption region includes a base region contacting the doped layer, a first facet region positioned on the base region, and a second facet region positioned on the first facet region. The first facet region includes (i) a first tapered surface and a second tapered surface extending from the base region and (ii) a first step region and a second step region extending laterally from the first tapered surface and the second tapered surface, respectively. The second facet region includes a third tapered surface extending from the first step region and a fourth tapered surface extending from the second step region.

公开(公告)号：US20230030971A1

公开(公告)日：2023-02-02

申请号：US17443891

申请日：2021-07-28

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar K. PATEL ,  Ming Gai Stanley LO ,  Xunyuan ZHANG

IPC: G02F1/225 ,  G02F1/015

Abstract: Embodiments presented in this disclosure generally relate to optical signal processing. More specifically, embodiments disclosed herein are directed to a semiconductor-insulator-semiconductor capacitor (SISCAP) modulator. One embodiment includes an optical modulator having a capacitive element configured to modulate an optical signal. The capacitive element includes a single-crystal semiconductor layer, a silicon germanium layer, and a dielectric region between the single-crystal semiconductor layer and the silicon germanium layer.

公开(公告)号：US20210263351A1

公开(公告)日：2021-08-26

申请号：US17302632

申请日：2021-05-07

Applicant: Cisco Technology, Inc.

Inventor： Xunyuan ZHANG ,  Vipulkumar K. PATEL ,  Prakash B. GOTHOSKAR ,  Ming Gai Stanley LO

IPC: G02F1/025

Abstract: Embodiments provide for an optical modulator, comprising: a lower guide, comprising: a lower hub, made of monocrystalline silicon; and a lower ridge, made of monocrystalline silicon that extends in a first direction from the lower hub; an upper guide, including: an upper hub; and an upper ridge, made of monocrystalline silicon that extends in a second direction, opposite of the first direction, from the upper hub and is aligned with the lower ridge; and a gate oxide layer separating the lower ridge from the upper ridge and defining a waveguide region with the lower guide and the upper guide.

公开(公告)号：US20210072460A1

公开(公告)日：2021-03-11

申请号：US16565203

申请日：2019-09-09

Applicant: Cisco Technology, Inc.

Inventor： Xunyuan ZHANG

IPC: G02B6/136

Abstract: Aspects described herein include a method of fabricating an optical apparatus. The method comprises etching a plurality of trenches partly through a first optical waveguide formed in a first semiconductor layer, wherein a first ridge is formed in the first optical waveguide between adjacent trenches of the plurality of trenches. The method further comprises conformally depositing a spacer layer above the first optical waveguide, wherein spacers are formed on sidewalls of each trench of the plurality of trenches. The method further comprises etching through the spacer layer to expose a respective bottom of each trench, wherein, for each respective bottom, a width of the respective bottom is defined by the spacers formed on the sidewalls of the trench corresponding to the respective bottom. The method further comprises depositing a first dielectric layer above the first optical waveguide, wherein dielectric material extends to the respective bottom of each trench.

公开(公告)号：US20200158949A1

公开(公告)日：2020-05-21

申请号：US16198251

申请日：2018-11-21

Applicant: Cisco Technology, Inc.

Inventor： Xunyuan ZHANG ,  Vipulkumar K. PATEL ,  Prakash B. GOTHOSKAR

IPC: G02B6/122 ,  G02B6/136

Abstract: A method of fabricating an optical apparatus comprises forming a first waveguide on a dielectric substrate. The first waveguide extends in a direction of an optical path. The first waveguide comprises a monocrystalline semiconductor material and is doped with a first conductivity type. The method further comprises depositing a first dielectric layer on the first waveguide, etching a first opening that extends at least partly through the first dielectric layer, and forming a second waveguide at least partly overlapping the first waveguide along the direction. The second waveguide is doped with a different, second conductivity type. Forming the second waveguide comprises depositing a monocrystalline semiconductor material on the first dielectric layer, whereby the first opening is filled with the deposited monocrystalline semiconductor material.

公开(公告)号：US20240085628A1

公开(公告)日：2024-03-14

申请号：US18507873

申请日：2023-11-13

Applicant: Cisco Technology, Inc.

Inventor： Xunyuan ZHANG

IPC: G02B6/136

CPC classification number: G02B6/136 ,  G02B2006/12097

Abstract: Aspects described herein include an optical apparatus. The optical apparatus includes a first optical waveguide formed in a first semiconductor layer and a second optical waveguide formed in a second semiconductor layer and separated from the first optical waveguide by a dielectric layer. The first optical waveguide extends in a direction of an optical path. The first optical waveguide and the second optical waveguide are at least partly overlapping along the direction. At least the first optical waveguide has a first ridge extending along the direction. The first ridge defined between spacers having a predetermined width.

公开(公告)号：US20200301176A1

公开(公告)日：2020-09-24

申请号：US16356982

申请日：2019-03-18

Applicant: Cisco Technology, Inc.

Inventor： Xunyuan ZHANG ,  Vipulkumar K. PATEL ,  Prakash B. GOTHOSKAR ,  Ming Gai Stanley LO

IPC: G02F1/025

Abstract: Embodiments provide for an optical modulator, comprising: a lower guide, comprising: a lower hub, made of monocrystalline silicon; and a lower ridge, made of monocrystalline silicon that extends in a first direction from the lower hub; an upper guide, including: an upper hub; and an upper ridge, made of monocrystalline silicon that extends in a second direction, opposite of the first direction, from the upper hub and is aligned with the lower ridge; and a gate oxide layer separating the lower ridge from the upper ridge and defining a waveguide region with the lower guide and the upper guide.

公开(公告)号：US20230290898A1

公开(公告)日：2023-09-14

申请号：US18318593

申请日：2023-05-16

Applicant: Cisco Technology, Inc.

Inventor： Xunyuan ZHANG ,  Li LI ,  Prakash B. GOTHOSKAR ,  Soha NAMNABAT

IPC: H01L31/18 ,  H01L31/0368 ,  H01L31/105 ,  H01L31/036

CPC classification number: H01L31/1812 ,  H01L31/03682 ,  H01L31/105 ,  H01L31/1892 ,  H01L31/1808 ,  H01L31/036

Abstract: The embodiments of the present disclosure describe a stressed Ge PD and fabrications techniques for making the same. In one embodiment, a stressor material is deposited underneath an already formed Ge PD. To do so, wafer bonding can be used to bond the wafer containing the Ge PD to a second, handler wafer. Doing so provides support to remove the substrate of the wafer so that a stressor material (e.g., silicon nitride, diamond-like carbon, or silicon-germanium) can be disposed underneath the Ge PD. The stress material induces a stress or strain in the crystal lattice of the Ge which changes its bandgap and improves its responsivity.

公开(公告)号：US20230022612A1

公开(公告)日：2023-01-26

申请号：US17443280

申请日：2021-07-23

Applicant: Cisco Technology, Inc.

Inventor： Xunyuan ZHANG ,  Ravi S. TUMMIDI ,  Tony P. POLOUS ,  Mark A. WEBSTER

IPC: G01M11/00 ,  G02B6/12

Abstract: Electrical test of optical components via metal-insulator-semiconductor capacitor structures is provided via a plurality of optical devices including a first material embedded in a second material, wherein each optical device is associated with a different thickness range of a plurality of thickness ranges for the first material; a first capacitance measurement point including the first material embedded in the second material; and a second capacitance measurement point including a region from which the first material has been replaced with the second material.