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59 条记录 (耗时 0.022 秒)

    Quantifying a difference between nodal voltages
    1.
    发明授权
    Quantifying a difference between nodal voltages 有权
    量化节点电压之间的差异

    公开(公告)号：US06806698B2

    公开(公告)日：2004-10-19

    申请号：US10078945

    申请日：2002-02-19

    申请人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Dean Liu ,  Kamran Zarrineh ,  Pradeep Trivedi

    发明人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Dean Liu ,  Kamran Zarrineh ,  Pradeep Trivedi

    IPC分类号： G01R2314

    CPC分类号： H03M1/0621 ,  G01K7/01 ,  G01K7/32 ,  H03M1/60

    摘要： A method and apparatus that uses the difference between two nodal voltages, such as a temperature-independent voltage and a temperature-dependent voltage, to determine the actual temperature at a point on an integrated circuit is provided. Further, a method and apparatus that converts a difference between nodal voltages in an integrated circuit from an analog to a digital quantity on the integrated circuit such that the difference in voltage may be used by an on-chip digital system is provided. Further, a method and apparatus for quantifying a difference in voltage between a first node and a second node of a temperature sensor is provided.

    摘要翻译： 提供了使用两个节点电压之间的差异的方法和装置，例如与温度无关的电压和与温度有关的电压，以确定集成电路上的点处的实际温度。 此外，提供了一种将集成电路中的节点电压与集成电路中的数字量之间的差异转换为使得片上数字系统可以使用电压差的方法和装置。 此外，提供了用于量化温度传感器的第一节点和第二节点之间的电压差的方法和装置。

    Low voltage temperature-independent and temperature-dependent voltage generator
    3.
    发明授权
    Low voltage temperature-independent and temperature-dependent voltage generator 有权
    低电压温度独立和温度依赖性电压发生器

    公开(公告)号：US06605988B1

    公开(公告)日：2003-08-12

    申请号：US10078140

    申请日：2002-02-19

    申请人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Kamran Zarrineh

    发明人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Kamran Zarrineh

    IPC分类号： G05F146

    CPC分类号： G05F3/30

    摘要： A method for using a low voltage power supply to generate a temperature-independent voltage and temperature-dependent voltage is provided. Further, an apparatus that uses a low voltage power supply to generate a temperature-independent voltage and temperature-dependent voltage is provided. The apparatus generates a temperature-dependent voltage and a temperature-independent voltage using an amplifier stage that generates a feedback signal; a startup stage that generates a startup signal dependent on the feedback signal; and an output stage that outputs the temperature-dependent voltage and the temperature-independent voltage dependent on the feedback and startup signals.

    摘要翻译： 提供一种使用低电压电源来产生与温度无关的电压和温度相关电压的方法。 此外，提供了使用低电压电源来产生与温度无关的电压和温度相关电压的装置。 该装置使用产生反馈信号的放大器级产生温度依赖电压和与温度无关的电压; 启动阶段，其根据反馈信号产生启动信号; 以及根据反馈和启动信号输出与温度有关的电压和独立于温度的电压的输出级。

    Adjustment and calibration system for post-fabrication treatment of on-chip temperature sensor
    4.
    发明授权
    Adjustment and calibration system for post-fabrication treatment of on-chip temperature sensor 失效
    片上温度传感器后处理调整校准系统

    公开(公告)号：US06749335B2

    公开(公告)日：2004-06-15

    申请号：US10147937

    申请日：2002-05-17

    申请人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Pradeep Trivedi ,  Lynn Ooi

    发明人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Pradeep Trivedi ,  Lynn Ooi

    IPC分类号： G01K1500

    CPC分类号： G01K15/00

    摘要： An adjustment and calibration system for post-fabrication treatment of an on-chip temperature sensor is provided. As explained in detail below, the adjustment and calibration system includes at least one adjustment circuit, to which the on-chip temperature sensor is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

    摘要翻译： 提供了一种用于片上温度传感器的后制造处理的调整和校准系统。 如下面详细说明的那样，调整和校准系统包括片上温度传感器响应于的至少一个调整电路，以及存储装置，其选择性地存储与调整电路的状态相关的控制信息（1）和 /或（2）从存储装置中写入这种控制信息的测试者，随后选择性地读出存储在存储装置中的控制信息，以便将调节电路调整到与控制信息相对应的状态。

    Post-silicon control of an embedded temperature sensor
    5.
    发明授权
    Post-silicon control of an embedded temperature sensor 有权
    嵌入式温度传感器的硅后控制

    公开(公告)号：US06775638B2

    公开(公告)日：2004-08-10

    申请号：US10131287

    申请日：2002-04-24

    申请人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Pradeep Trivedi ,  Lynn Ooi

    发明人： Claude Gauthier ,  Brian Amick ,  Spencer Gold ,  Pradeep Trivedi ,  Lynn Ooi

    IPC分类号： G01K100

    CPC分类号： G01K15/00

    摘要： A temperature sensor adapted to produce a temperature-independent voltage and temperature-dependent voltage dependent on an internal control signal, generated within the temperature sensor, adjustable by an adjustment circuit operatively connected to the temperature sensor is provided. The adjustment circuit is controllable to adjust the internal control signal in order to modify an operating characteristic of the temperature sensor.

    摘要翻译： 提供了一种温度传感器，其适于根据可操作地连接到温度传感器的调节电路可调节地产生取决于温度传感器内产生的内部控制信号的与温度无关的电压和温度依赖电压。 调节电路可以调节内部控制信号，以便改变温度传感器的工作特性。

    I/O interface anti-resonance passband shunting technique
    6.
    发明授权
    I/O interface anti-resonance passband shunting technique 有权
    I / O接口反共振通带分流技术

    公开(公告)号：US06909203B2

    公开(公告)日：2005-06-21

    申请号：US10356905

    申请日：2003-02-03

    申请人： Claude Gauthier ,  Brian Amick ,  Aninda Roy

    发明人： Claude Gauthier ,  Brian Amick ,  Aninda Roy

    IPC分类号： G06F1/26 ,  H02H7/00 ,  A01H79/00

    CPC分类号： G06F1/26 ,  Y10T307/398

    摘要： A method and apparatus for regulating resonance in a computer system I/O interface is provided. A shunting impedance/resistance is arranged across a power supply of the I/O interface. The shunting impedance/resistance is controlled by circuitry that is arranged to detect voltage overshoot conditions in the I/O interface. The circuitry has (1) an analog front end that is arranged to detect power supply oscillations relative to a grounded terminal, (2) an amplifier (or logic conversion circuit) that is arranged to convert an output signal from the analog front end to a digital signal, and (3) a shunting apparatus arranged to modify power supply behavior in the I/O interface dependent on the digital signal.

    摘要翻译： 提供了一种用于调节计算机系统I / O接口中的共振的方法和装置。 在I / O接口的电源上布置分流阻抗/电阻。 分流阻抗/电阻由设置为检测I / O接口中的电压过冲条件的电路控制。 电路具有（1）模拟前端，其被配置为检测相对于接地端子的电源振荡，（2）放大器（或逻辑转换电路），其被布置为将来自模拟前端的输出信号转换为 数字信号，以及（3）分配装置，其被配置为根据数字信号修改I / O接口中的电源行为。

    Chip/package resonance damping using controlled package series resistance
    7.
    发明授权
    Chip/package resonance damping using controlled package series resistance 有权
    芯片/封装谐振阻尼采用受控封装串联电阻

    公开(公告)号：US06822345B2

    公开(公告)日：2004-11-23

    申请号：US10118840

    申请日：2002-04-09

    申请人： Claude Gauthier ,  Brian Amick

    发明人： Claude Gauthier ,  Brian Amick

    IPC分类号： H02J700

    CPC分类号： H01L23/5286 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T307/615 ,  H01L2924/00

    摘要： A method and apparatus for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least one resistive element connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path.

    摘要翻译： 提供一种用于降低集成电路的电源路径的阻抗的方法和装置。 电源路径包括第一电源线和向集成电路提供电力的第二电源线。 连接在第一电源线和第二电源线之间的至少一个电阻元件被调节以减小电源路径的阻抗。

    Phase locked loop input receiver design with delay matching feature
    8.
    发明授权
    Phase locked loop input receiver design with delay matching feature 有权
    锁相环输入接收机设计具有延迟匹配功能

    公开(公告)号：US06778027B2

    公开(公告)日：2004-08-17

    申请号：US10121806

    申请日：2002-04-12

    申请人： Claude Gauthier ,  Pradeep Trivedi ,  Brian Amick

    发明人： Claude Gauthier ,  Pradeep Trivedi ,  Brian Amick

    IPC分类号： H03L700

    CPC分类号： G06F1/10 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/18

    摘要： A phase locked loop that includes a receiver circuit for matching delays of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver circuit employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry control the generation of substantially delay matched system and feedback clocks.

    摘要翻译： 提供了一种锁相环，其包括用于在系统时钟的延迟和在锁相环的输入处的反馈时钟的匹配的接收器电路。 接收器电路采用系统时钟路径电路来输入系统时钟和反馈时钟路径电路以输入反馈时钟，其中与系统时钟路径电路相关联的电流和负载电阻以及与反馈时钟路径电路相关联的电流和负载电阻 控制生成基本上延迟匹配的系统和反馈时钟。

    Programmable bias-generator for self-biasing a delay locked loop
    9.
    发明授权
    Programmable bias-generator for self-biasing a delay locked loop 有权
    用于自偏置延迟锁定环的可编程偏置发生器

    公开(公告)号：US06597218B1

    公开(公告)日：2003-07-22

    申请号：US10131308

    申请日：2002-04-24

    申请人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    发明人： Claude Gauthier ,  Brian Amick ,  Dean Liu ,  Pradeep Trivedi

    IPC分类号： H03L706

    CPC分类号： H03L7/0891 ,  H03L7/0812 ,  Y10S331/02

    摘要： A technique Readjusting a bias-generator in a delay locked loop after fabrication of the delay locked loop. The technique involves use of an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated.

    摘要翻译： 一种技术在制造延迟锁定环路后，在延迟锁定环路中重新调整偏置发生器。 该技术涉及使用可操作地连接到偏置发生器的调节电路，其中调节电路是可控制的，以便于修正偏置发生器的电压输出。 由偏置发生器输出的电压的这种控制允许设计者在制造延迟锁定环路之后实现期望的延迟锁定环路性能特性。

    Digital delay locked loop with extended phase capture range
    10.
    发明授权
    Digital delay locked loop with extended phase capture range 有权
    具延时相位捕捉范围的数字延迟锁定环

    公开(公告)号：US07107475B1

    公开(公告)日：2006-09-12

    申请号：US10690302

    申请日：2003-10-21

    申请人： Brian Amick ,  Dong Joon Yoon ,  Tri Tran ,  Gajendra Singh ,  Aparna Ramachandran ,  Claude Gauthier

    发明人： Brian Amick ,  Dong Joon Yoon ,  Tri Tran ,  Gajendra Singh ,  Aparna Ramachandran ,  Claude Gauthier

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12 ,  H03K2005/00241 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/10

    摘要： A digital delay locked loop uses a delay array to delay an input signal by an amount indicated by a delay code. A phase of the resulting delayed signal is compared to a corresponding phase of the input signal, and dependent on the comparison, the delay code is updated to indicate whether the delay array needs to provide more delay or less delay. The digital delay locked loop also uses a detection circuit that monitors for a predetermined condition of the delay code. In response to detection of the predetermined condition, the delay code is automatically reset to a value different than a value of the delay code present at a previous reset or initial startup of the digital delay locked loop.

    摘要翻译： 数字延迟锁定环使用延迟阵列将输入信号延迟由延迟码指示的量。 将所得到的延迟信号的相位与输入信号的相应相位进行比较，并且根据比较，更新延迟码以指示延迟阵列是否需要提供更多的延迟或更小的延迟。 数字延迟锁定环路还使用监视延迟码的预定条件的检测电路。 响应于预定条件的检测，延迟码被自动复位到与数字延迟锁定环的先前复位或初始启动时存在的延迟码的值不同的值。