公开(公告)号：US06177807B1

公开(公告)日：2001-01-23

申请号：US09322465

申请日：1999-05-28

申请人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

发明人： Claude L. Bertin ,  John A. Fifield ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

IPC分类号： G03K1716

CPC分类号： G06F13/4086 ,  H03K5/06 ,  H04L25/0298

摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.

摘要翻译： 具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。 数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。 具有递增可变长度的传输线短截线连接到控制线14的存储器控​​制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路 在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。

公开(公告)号：US06812122B2

公开(公告)日：2004-11-02

申请号：US10095889

申请日：2002-03-12

申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

IPC分类号： H01L2144

CPC分类号： H01L21/763 ,  H01L23/5252 ,  H01L27/10861 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for forming a first one time, voltage programmable logic element in a semiconductor substrate of first conductivity type, forming a first layer beneath a surface of the substrate, the first layer having a second conductivity type. A trench is formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench.

摘要翻译： 用于形成第一导电类型的半导体衬底中的第一次电压可编程逻辑元件的方法，在所述衬底的表面下方形成第一层，所述第一层具有第二导电类型。 沟槽通过表面形成并穿过第一层。 沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。 第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。

公开(公告)号：US06388305B1

公开(公告)日：2002-05-14

申请号：US09466495

申请日：1999-12-17

申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  Max G. Levy ,  Rick L. Mohler ,  William R. Tonti ,  Wayne M. Trickle

IPC分类号： H01L2900

CPC分类号： H01L21/763 ,  H01L23/5252 ,  H01L27/10861 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer beneath a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a dielectric material lining the interior surface and a conductive material filling the lined trench. The first logic element is configured so that a predetermined voltage or higher applied between the conductive material and the first layer causes a breakdown within a region of the trench. A second one time, voltage programmable logic element is provided in a semiconductor substrate of first conductivity type that comprises a first layer formed in a surface of the substrate, the first layer having a second conductivity type; and a trench formed through the surface and passing through the first layer. The trench comprises an interior surface, a first dielectric material lining the interior surface and a second dielectric material filling the lined trench. The second logic element further comprises a dielectric layer formed over a portion of the first layer and contacting the first dielectric material lining the trench at a merge location; and an electrode extending over a portion of both the dielectric layer and the filled trench. The second logic element is configured so that a predetermined voltage or higher applied between the electrode and the first layer causes a breakdown near the merge location.

摘要翻译： 首先，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该第一导电类型的半导体衬底包括在衬底的表面下面的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。 沟槽包括内表面，衬在内表面的电介质材料和填充衬里沟槽的导电材料。 第一逻辑元件被配置为使得施加在导电材料和第一层之间的预定电压或更高的电压导致沟槽区域内的击穿。 第二次，电压可编程逻辑元件设置在第一导电类型的半导体衬底中，该半导体衬底包括形成在衬底的表面中的第一层，第一层具有第二导电类型; 以及通过表面形成并穿过第一层的沟槽。 沟槽包括内表面，衬在内表面的第一电介质材料和填充衬里沟槽的第二电介质材料。 第二逻辑元件还包括形成在第一层的一部分上并且在合并位置处接触衬套在沟槽上的第一介电材料的电介质层; 以及在电介质层和填充沟槽的一部分上延伸的电极。 第二逻辑元件被配置为使得施加在电极和第一层之间的预定电压或更高的电压导致合并位置附近的击穿。

公开(公告)号：US06574763B1

公开(公告)日：2003-06-03

申请号：US09473886

申请日：1999-12-28

申请人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

发明人： Claude L. Bertin ,  Erik L. Hedberg ,  Russell J. Houghton ,  William R. Tonti

IPC分类号： G01R3128

CPC分类号： G01R31/287

摘要： A burn-in process is provided for a memory array having redundant bits and addressable storage locations. The burn-in process includes the steps of raising the temperature of the memory array to a pre-determined temperature, testing all bits in the array, detecting faulty bits and operable bits, replacing faulty bits with redundant operable bits, correcting any defects in the array in-situ, and lowering the temperature of the memory array to ambient temperature to complete the burn-in process. An apparatus for carrying out the above process is provided that includes a test circuit for generating a test pattern and for applying the test pattern to the memory array so as to test all bits within the memory array. A comparison circuit, coupled to the test circuit and adapted to couple to the memory array, compares an actual response and an expected response of the memory array to the test pattern and detects faulty and operable bits based thereon. A failed address buffer register, coupled to the comparison circuit and to the test circuit, stores an address of each addressable storage location that has a faulty bit. Sparing control logic, coupled to the failed address buffer register and adapted to couple to the memory array, reads out each address stored by the failed address buffer register and replaces each faulty bit with a redundant operable bit.

摘要翻译： 为具有冗余位和可寻址存储位置的存储器阵列提供老化过程。 老化过程包括以下步骤：将存储器阵列的温度升高到预定温度，测试阵列中的所有位，检测故障位和可操作位，用冗余的可操作位代替故障位，校正在 阵列原位，并将存储器阵列的温度降低到环境温度以完成老化过程。 提供了一种用于执行上述处理的装置，其包括用于生成测试图案并将测试图案应用于存储器阵列的测试电路，以便测试存储器阵列内的所有位。 耦合到测试电路并且适于耦合到存储器阵列的比较电路将存储器阵列的实际响应和预期响应与测试模式进行比较，并基于此检测故障和可操作的位。 耦合到比较电路和测试电路的故障地址缓冲寄存器存储具有错误位的每个可寻址存储位置的地址。 冗余控制逻辑耦合到故障地址缓冲寄存器并适于耦合到存储器阵列，读出由故障地址缓冲寄存器存储的每个地址，并用冗余可操作位替换每个故障位。

公开(公告)号：US06346846B1

公开(公告)日：2002-02-12

申请号：US09466479

申请日：1999-12-17

申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  William R. Tonti ,  Nicholas M. Van Heel

发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  William R. Tonti ,  Nicholas M. Van Heel

IPC分类号： H01H3776

CPC分类号： G11C5/145 ,  G11C17/18

摘要： Methods and apparatus for blowing and sensing antifuses are provided. Specifically, in a first aspect, a method is provided for changing the state of one of a plurality of antifuses by selecting one of the bank of antifuses and applying a high voltage to change the state of the selected antifuse. In second and third aspects, apparatus are provided for performing the method of the first aspect. In a fourth aspect, a method is provided for boosting a voltage that includes the steps of generating a first voltage within a first stage storage mechanism of a first stage voltage booster circuit, generating a second voltage equaling about twice the first voltage within a first and a second, second stage storage mechanism of a second stage voltage booster circuit, and generating about thrice the first voltage based on the second voltage of the second stage voltage booster circuit. In a fifth aspect, apparatus are provided for performing the method of the fourth aspect.

摘要翻译： 提供了用于吹制和检测反熔丝的方法和装置。 具体地，在第一方面中，提供一种通过选择一组反熔丝中的一个并且施加高电压来改变所选择的反熔丝的状态来改变多个反熔丝之一的状态的方法。 在第二和第三方面中，提供了用于执行第一方面的方法的装置。 在第四方面，提供了一种用于升压电压的方法，包括以下步骤：在第一级升压电路的第一级存储机构内产生第一电压，产生等于第一级升压电路中第一电压的大约两倍的第二电压， 第二级升压电路的第二级第二级存储机构，并且基于第二级升压电路的第二电压产生约三倍的第一电压。 在第五方面中，提供了用于执行第四方面的方法的装置。

公开(公告)号：US06195027B1

公开(公告)日：2001-02-27

申请号：US09302744

申请日：1999-04-30

申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  Steven W. Tomashot ,  William R. Tonti

发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  Steven W. Tomashot ,  William R. Tonti

IPC分类号： H03M720

CPC分类号： G11C8/10

摘要： A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.

摘要翻译： 提供了用于将n个输入信号及其与m个输出信号之一的补码进行解码的方法和结构。 提供具有m个输出节点的电容网络。 输出节点预充电到给定的电压值。 提供N个输入信号及其补码，每个具有高值或低值。 响应于输入信号的真值和补码值的给定输入模式，至少一个但不到所有输出节点的输出模式被放电到小于给定电压但大于输出模式的输出值的值。 放电节点的输出模式是为任何给定模式的输入信号提供一个且仅一个放电或一个且仅一个未充电节点。 优选地，电容网络包括NMOS反转电容器。

公开(公告)号：US5761114A

公开(公告)日：1998-06-02

申请号：US803034

申请日：1997-02-19

申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

IPC分类号： G11C11/56

CPC分类号： G11C11/565 ,  G11C16/30

摘要： A method and apparatus for using multi-level signals in a gain cell is shown. The method involves of first, storing a value of a multi-level signal in the gain cell. A stepping waveform is then applied to the gain cell and the gain cell outputs a conduction signal when the level of the stepping waveform corresponds to the value of the multilevel signal that is stored within the gain cell. Finally, the value of the multi-level signal is determined through the conduction signal and the corresponding level of the stepping waveform. The gain cell includes an input device, a storage device and a level comparator, which responds to the stepping waveform generated from a stepping signal generator and outputs the conduction signal for determining the value of the multi-level signal stored in the storage device.

摘要翻译： 示出了在增益单元中使用多电平信号的方法和装置。 该方法首先在增益单元中存储多电平信号的值。 然后，当增益单元的步进波形对应于存储在增益单元内的多电平信号的值时，增益单元输出导通信号。 最后，通过导通信号和步进波形的相应电平来确定多电平信号的值。 增益单元包括响应于从步进信号发生器产生的步进波形的输入装置，存储装置和电平比较器，并输出用于确定存储在存储装置中的多电平信号的值的导通信号。

公开(公告)号：US06268748B1

公开(公告)日：2001-07-31

申请号：US09073517

申请日：1998-05-06

申请人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

发明人： Claude L. Bertin ,  John A. Fifield ,  Russell J. Houghton ,  Christopher P. Miller ,  William R. Tonti

IPC分类号： G03K19094

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  H03K19/0016 ,  H03K19/09429

摘要： An electronic semiconductor module, either memory or logic, having a driver circuit which includes a multiplicity of driver transistors, together with circuitry for simultaneously applying a first positive bias to a first select number of driver transistors to activate them to an operational state, a second positive bias to a second select number of driver transistors to place them in readiness for activation, and a negative bias to the remaining driver transistors to place them in a fully inactive state thereby reducing noise in the driver circuit. The first positive bias is greater than the transistor threshold voltage, preferably greater than two volts, the second positive bias is less than the threshold voltage, preferably less than one volt, and the negative bias is in the order of minus 0.3 volt. A method of reducing noise in the electronic semiconductor module is also described and includes the applying of a positive bias to a first select number of the transistors to activate them while simultaneously applying a second positive bias to a second select number of the transistors to ready them for activation, and a negative voltage to the remaining transistors to place each in a inactive condition.

摘要翻译： 一种电子半导体模块，无论是存储器还是逻辑，具有包括多个驱动器晶体管的驱动器电路，以及用于同时向第一选择数量的驱动器晶体管施加第一正偏置以将其激活到操作状态的电路，第二 对第二选择数量的驱动器晶体管施加正偏置以使它们准备激活，以及对其余驱动器晶体管的负偏置以将它们置于完全无效状态，从而降低驱动器电路中的噪声。 第一正偏压大于晶体管阈值电压，优选大于2伏，第二正偏压小于阈值电压，优选小于1伏特，负偏压为零下0.3伏。 还描述了降低电子半导体模块中的噪声的方法，并且包括将正偏压施加到第一选择数量的晶体管以激活它们，同时向第二选择数量的晶体管施加第二正偏置以准备它们 用于激活，并且向剩余晶体管施加负电压以使其处于非活动状态。

公开(公告)号：US5757693A

公开(公告)日：1998-05-26

申请号：US803056

申请日：1997-02-19

申请人： Russell J. Houghton ,  Claude L. Bertin ,  John A. Fifield ,  Christopher P. Miller ,  William R. Tonti

发明人： Russell J. Houghton ,  Claude L. Bertin ,  John A. Fifield ,  Christopher P. Miller ,  William R. Tonti

IPC分类号： G11C11/402 ,  G11C11/403 ,  G11C11/405 ,  G11C11/24

CPC分类号： G11C11/405 ,  G11C11/403

摘要： A gain cell in a memory array having read and write bitlines and wordlines, wherein the gain cell comprises a write transistor, a storage node, a read transistor, and a diode is disclosed. The write transistor allows the value of the write bitline to be stored onto the storage node when activated by the write wordline. The read transistor, which allows the stored value to be read, is coupled to the storage node and to the read bitline via the diode. The diode prevents the conduction of the read transistor in the opposite direction, thus preventing read interference from other cells and reducing bitline capacitance.

摘要翻译： 具有读和写位线和字线的存储器阵列中的增益单元，其中增益单元包括写晶体管，存储节点，读晶体管和二极管。 当由写入字线激活时，写入晶体管允许将写入位线的值存储到存储节点上。 允许读取存储值的读取晶体管通过二极管耦合到存储节点和读取位线。 二极管防止读取晶体管在相反方向的导通，从而防止来自其他单元的读取干扰并减少位线电容。

公开(公告)号：US06233184B1

公开(公告)日：2001-05-15

申请号：US09191954

申请日：1998-11-13

申请人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

发明人： John E. Barth ,  Claude L. Bertin ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  William R. Tonti ,  Donald L. Wheater

IPC分类号： G11C2900

CPC分类号： G01R31/2855 ,  G01R31/2806 ,  G01R31/2831 ,  G01R31/31905 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00014

摘要： Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.

摘要翻译： 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接，并且每个测试引擎可以连接到多个芯片，例如晶片上的行或一列芯片。 因此，仍然提供必须连接用于测试的晶片的焊盘数量，同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余，以便在老化完成后可以修复故障的芯片。 此外，可编程测试引擎可以对其代码进行更改，因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号，为阵列提供更高的有效电压，从而降低老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开，因此短路芯片可以断开。 优选地，膜在测试之后保留在晶片上，老化和切割以提供芯片级封装。 因此，避免了TCE匹配材料（例如玻璃陶瓷接触器）用于晶片老化的非常高的成本，同时提供超出测试和包装封装的优点。