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1.发明授权Integrated semiconductor memory and method for operating a semiconductor memory 失效用于操作半导体存储器的集成半导体存储器和方法公开(公告)号：US07443713B2
公开(公告)日：2008-10-28
申请号：US11331365
申请日：2006-01-13
IPC分类号： G11C11/02
CPC分类号： G11C11/404 , H01L27/10885
摘要： An integrated semiconductor memory device includes at least one memory cell, at least one sense amplifier and a pair of bit lines connected to each sense amplifier, where each memory cell includes a selection transistor and a storage capacitor. The storage capacitor of each memory cell includes a first capacitor electrode and a second capacitor electrode, and the selection transistor of each memory cell includes a first source/drain region that is connected by a first contact connection to one bit line of a pair of bit lines corresponding with the memory cell, and a second source/drain region that is conductively connected to the first capacitor electrode of the storage capacitor of the memory cell. The second capacitor electrode of the storage capacitor of each memory cell is connected to the other bit line of the pair of bit lines corresponding with the memory cell.
摘要翻译： 集成半导体存储器件包括至少一个存储器单元，至少一个读出放大器和连接到每个读出放大器的一对位线，其中每个存储器单元包括选择晶体管和存储电容器。 每个存储单元的存储电容器包括第一电容器电极和第二电容器电极，并且每个存储单元的选择晶体管包括通过第一接触连接连接到一对位的一个位线的第一源极/漏极区域 与存储单元相对应的线，以及与存储单元的存储电容器的第一电容电极导电连接的第二源/漏区。 每个存储单元的存储电容器的第二电容器电极连接到与存储单元相对应的一对位线的另一位线。
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2.发明授权Integrated semiconductor memory and method for electrically stressing an integrated semiconductor memory 失效集成半导体存储器和用于电应力集成半导体存储器的方法公开(公告)号：US07482644B2
公开(公告)日：2009-01-27
申请号：US11061087
申请日：2005-02-18
IPC分类号： H01L29/73
CPC分类号： G11C29/025 , G11C29/02 , H01L27/105 , H01L27/10891
摘要： Semiconductor memories (1) have segmented word lines (5a, 5b), which in each case have a main word line (10a, 10b) made of a conductive metal and a plurality of interconnect segments (15a, 15b) coupled to the main word line (10a, 10b), which are coupled to the respective main word line (10a, 10b) in each case via at least one contact hole filling (11). If one of the contact hole fillings (11) is defective or at high resistance then functional errors of the semiconductor memory occur. The interconnect segments (15a, 15b) of two respective word lines (5a, 5b) can be short-circuited in pairs with the aid of switching units (20), whereby a static current (I) that flows via the contact hole fillings (11) can be used for electrically stressing the contact hole fillings (11). Electrical stressing of contact hole fillings of segmented word lines is thus made possible.
摘要翻译： 半导体存储器（1）具有分段字线（5a，5b），它们在每种情况下具有由导电金属制成的主字线（10a，10b）和耦合到主字的多个互连部分（15a，15b） 线路（10a，10b），其通过至少一个接触孔填充物（11）在每种情况下耦合到相应的主字线（10a，10b）。 如果接触孔填充物（11）中的一个有缺陷或高电阻，则会发生半导体存储器的功能错误。 两个相应字线（5a，5b）的互连部分（15a，15b）可以借助于开关单元（20）成对地短路，由此通过接触孔填充物流动的静电流（I） 11）可以用于电接触接触孔填充物（11）。 因此，分段字线的接触孔填充的电应力成为可能。
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3.发明申请Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells 有权包括至少一个字线并且包括多个存储单元的集成半导体存储器公开(公告)号：US20050281118A1
公开(公告)日：2005-12-22
申请号：US11140554
申请日：2005-05-27
IPC分类号： G11C8/00 , G11C8/08 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/02 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/4085 , G11C29/02 , G11C29/025 , G11C29/83 , G11C29/832 , G11C2029/1202 , H01L27/10891 , H01L27/10897
摘要： An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.
摘要翻译： 集成半导体存储器包括至少一个字线和多个存储器单元。 每个存储单元具有耦合到字线的选择晶体管。 字线驱动器耦合到字线。 字线驱动器向字线提供第一电位或第二电势，使得字线由第一电位激活并且被第二电位禁用。 无源部件（例如，二极管或电阻器）被耦合在字线和第二电势之间，使得字线通过无源部件以高电阻方式耦合到第二电位。 无源元件对于字线和触点连接之间的漏电流是透射的。
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4.发明授权Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells 有权包括至少一个字线并且包括多个存储单元的集成半导体存储器公开(公告)号：US07180820B2
公开(公告)日：2007-02-20
申请号：US11140554
申请日：2005-05-27
IPC分类号： G11C8/00
CPC分类号： G11C11/4085 , G11C29/02 , G11C29/025 , G11C29/83 , G11C29/832 , G11C2029/1202 , H01L27/10891 , H01L27/10897
摘要： An integrated semiconductor memory includes at least one word line and a number of memory cells. Each memory cell has a selection transistor coupled to the word line. A word line driver is coupled to the word line. The word line driver provides a first electrical potential or a second electrical potential to the word line such that the word line is activated by the first electrical potential and is deactivated by the second electrical potential. A passive component (e.g., a diode or a resistor) is coupled between the word line and the second electrical potential such that the word line is coupled to the second electrical potential in a high-resistance fashion through the passive component. The passive component is transmissive for a leakage current between the word line and the contact connection.
摘要翻译： 集成半导体存储器包括至少一个字线和多个存储器单元。 每个存储单元具有耦合到字线的选择晶体管。 字线驱动器耦合到字线。 字线驱动器向字线提供第一电位或第二电势，使得字线由第一电位激活并且被第二电位禁用。 无源部件（例如，二极管或电阻器）被耦合在字线和第二电势之间，使得字线通过无源部件以高电阻方式耦合到第二电位。 无源元件对于字线和触点连接之间的漏电流是透射的。
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5.发明授权Integrated semiconductor memory device and method for operating an integrated semiconductor memory device 有权用于操作集成半导体存储器件的集成半导体存储器件和方法公开(公告)号：US07102912B2
公开(公告)日：2006-09-05
申请号：US11071590
申请日：2005-03-04
IPC分类号： G11C11/00
CPC分类号： G11C11/4094 , G11C7/02 , G11C7/12
摘要： An integrated semiconductor memory device includes a memory cell array (B1) with a first bit line and a second bit line (BL, /BL), a controllable resistor (SW) and a control unit (100) configured to control the controllable resistor. In a first operating state of the integrated semiconductor memory device, the first and second bit lines are connected to one another via a first controllable switch (ET1) and also via the controllable resistor (SW) which has been set to a low resistance, to a connection (A10) that applies a mid-voltage (VBLEQ), where the voltage level of the mid-voltage is in the form of an arithmetic mean between a first and second voltage potential (VBLH, VBLL). By virtue of the control unit briefly setting the controllable resistor to a very low resistance in the first operating state of the integrated semiconductor memory device, the period of time required for the first and second bit lines require to assume the mid-voltage (VBLEQ) is shortened. The influence of capacitive coupling influences, which slow down the charging of the first and second bit lines to the mid-voltage, is significantly reduced as a result.
摘要翻译： 集成半导体存储器件包括具有第一位线和第二位线（BL，/ BL）的存储单元阵列（B 1），可控电阻器（SW）和控制单元（100），其被配置为控制可控电阻器 。 在集成半导体存储器件的第一操作状态下，第一和第二位线经由第一可控开关（ET 1）彼此连接，并且还经由设置为低电阻的可控电阻（SW）连接， 涉及施加中间电压（V BAT）的连接（A 10），其中中压的电压电平为第一和第二电压电位之间的算术平均值 VBLH，VBLL）。 由于控制单元在集成半导体存储器件的第一操作状态下将可控电阻短暂地设置为非常低的电阻，所以第一和第二位线所需的时间段需要采用中间电压（V < SUB> BLEQ ）缩短。 因此，将第一和第二位线的充电速度降低到中间电压的电容耦合影响的影响显着减小。
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公开(公告)号：US07266027B2
公开(公告)日：2007-09-04
申请号：US11235540
申请日：2005-09-27
IPC分类号： G11C7/00
CPC分类号： G11C29/025 , G11C8/08 , G11C11/401 , G11C29/02 , G11C2029/1202
摘要： An integrated semiconductor memory includes word lines connected to a first voltage potential via a respective first controllable switch and a respective third controllable switch and to a second voltage potential via a respective second controllable switch. In order to test whether one of the word lines is connected to the first voltage potential via its respective first and third controllable switches, the one of the word lines is connected to a comparator circuit via the respective second controllable switch and a driver line. After the respective first and third controllable switches have been controlled into the on state, in a test operating state of the integrated semiconductor memory, the respective second controllable switch is controlled into the on state and a potential state on the word line is evaluated by the comparator circuit. The result of the evaluation is fed to an external data terminal by an evaluation signal.
摘要翻译： 集成半导体存储器包括通过相应的第一可控开关和相应的第三可控开关连接到第一电压电位的字线，以及经由相应的第二可控开关连接到第二电压电位的字线。 为了测试字线之一是否经由其相应的第一和第三可控开关连接到第一电压电位，所述字线之一经由相应的第二可控开关和驱动器线连接到比较器电路。 在相应的第一和第三可控开关已经被控制为导通状态之后，在集成半导体存储器的测试操作状态下，将相应的第二可控开关控制在导通状态，并且字线上的电位状态由 比较器电路。 评估结果通过评估信号馈送到外部数据终端。
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7.发明授权Circuit arrangement and method for setting a voltage supply for a read/write amplifier of an integrated memory 失效用于设置集成存储器的读/写放大器的电压源的电路布置和方法公开(公告)号：US06999355B2
公开(公告)日：2006-02-14
申请号：US10841546
申请日：2004-05-10
CPC分类号： G11C11/4091 , G11C5/14 , G11C7/06 , G11C2207/065
摘要： A circuit arrangement for setting a voltage supply for a read/write amplifier of an integrated memory has a first voltage generator circuit for generating a supply voltage for application to the read/write amplifier during an assessment and amplification operation and a second voltage generator circuit for generating a precharge voltage for precharging bit lines of the memory which are connected to the read/write amplifier. A temperature detector circuit, which is connected to the first voltage generator circuit, is used to detect a temperature of the memory and interacts with the first voltage generator circuit to set the supply voltage applied to the read/write amplifier in a manner depending on a temperature of the memory.
摘要翻译： 用于设置用于集成存储器的读/写放大器的电压源的电路装置具有第一电压发生器电路，用于在评估和放大操作期间产生用于施加到读/写放大器的电源电压，以及第二电压发生器电路， 产生用于对连接到读/写放大器的存储器的位线进行预充电的预充电电压。 连接到第一电压发生器电路的温度检测器电路用于检测存储器的温度并与第一电压发生器电路相互作用以将施加到读/写放大器的电源电压设置为取决于 记忆温度
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8.发明申请Integrated semiconductor memory and method for operating a semiconductor memory 失效用于操作半导体存储器的集成半导体存储器和方法公开(公告)号：US20060193168A1
公开(公告)日：2006-08-31
申请号：US11331365
申请日：2006-01-13
CPC分类号： G11C11/404 , H01L27/10885
摘要： An integrated semiconductor memory device includes memory cells each with a selection transistor and a storage capacitor. Memory cells of this type are usually read by the potential of the bit line to which the memory cell is connected being compared in a sense amplifier with the potential of a complementary, second bit line and a voltage difference identified being amplified. The semiconductor memory according to the invention provides for that capacitor electrode which is not connected to the selection transistor to be connected to the complementary, second bit line. As a result, for an operating voltage with the same magnitude, larger quantities of charge can be stored in the storage capacitor since now the two mutually spread potentials output by the sense amplifier are used for biasing the storage capacitor. The resultant increase in the signal strength makes the semiconductor memory insensitive toward signal corruptions which arise for example in the case of operating voltages at different levels for selection transistors and for transistors in the signal amplifier.
摘要翻译： 集成半导体存储器件包括各自具有选择晶体管和存储电容器的存储单元。 这种类型的存储单元通常通过读出放大器中与存储器单元连接的位线的电位进行读取，其中互补的第二位线的电位和识别的电压差被放大。 根据本发明的半导体存储器提供了未连接到选择晶体管以连接到互补的第二位线的电容器电极。 结果，对于具有相同幅度的工作电压，由于现在由读出放大器输出的两个相互扩展的电位用于偏置存储电容器，所以可以将大量的电荷存储在存储电容器中。 信号强度的增加使得半导体存储器对信号损坏不敏感，例如在用于选择晶体管的不同电平的操作电压和信号放大器中的晶体管的情况下。
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公开(公告)号：US06556486B2
公开(公告)日：2003-04-29
申请号：US09998725
申请日：2001-11-30
申请人： Herbert Benzinger , Norbert Wirth , Ralf Schneider
发明人： Herbert Benzinger , Norbert Wirth , Ralf Schneider
IPC分类号： G11O1604
CPC分类号： G11C7/1006 , G11C7/22
摘要： A circuit configuration and a method for the synchronization of signals include transmitting signals in parallel through data lines and buffer-storing the signals in a synchronizing unit. A clock signal is determined from the signals of a data line and is used for synchronizing the outputting of the signals. The signals are output in the order in which the signals were read. The signals are likewise output through a plurality of data lines, the signals being output temporally synchronously. Propagation time differences are compensated due to the buffer-storage. Moreover, the clock signal is determined from the signals themselves. Consequently, the use of an additional clock signal is not necessary.
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10.发明申请Integrated semiconductor memory and method for operating an integrated semiconductor memory 有权用于操作集成半导体存储器的集成半导体存储器和方法公开(公告)号：US20060083100A1
公开(公告)日：2006-04-20
申请号：US11245455
申请日：2005-10-06
IPC分类号： G11C8/00
CPC分类号： G11C29/025 , G11C7/18 , G11C8/08 , G11C11/401 , G11C11/4085 , G11C11/4097 , G11C29/02 , G11C2029/1202
摘要： A semiconductor memory and a method for operating the latter in order are provided, at least in testwise fashion, to deactivate a word line segment (12) of a segmented word line not via a first line (21) otherwise used for deactivation, but rather via a second line (22) via that the word line segment (12) is otherwise activated. The second line (22) can optionally be biased with a second potential (Vpp) provided for activation or with a third potential (Vgnd). If the third potential (Vgnd) is used for at least temporarily deactivating the word line segment (12), the word line segment can be driven via a switching element (17), which couples the word line segment to the second line (22), without the complementary switching element (16) of the driver segment (20) having to be used for deactivation. It can thereby be ascertained which of two switching elements (16, 17) of the driver segment is defective and whether or not the semiconductor memory will function in a manner free of errors after permanent replacement of the word line on account of a floating potential of the tested word line segment (12).
摘要翻译： 至少以测试方式，提供半导体存储器和用于依次操作的方法，以不经由用于去激活的第一行（21）去激活分段字线的字线段（12），而是 经由第二行（22）经由字线段（12）被另外激活。 第二行（22）可以可选地被提供用于激活或第三电位（Vgnd）的第二电位（Vpp）偏置。 如果第三电位（Vgnd）用于至少暂时禁用字线段（12），则可以经由将字线段耦合到第二线路（22）的开关元件（17）来驱动字线段， ，而驱动器段（20）的互补开关元件（16）必须用于去激活。 因此，可以确定驱动器段的两个开关元件（16,17）中的哪一个有缺陷，以及由于浮动电位的永久替换字线，半导体存储器是否以没有错误的方式起作用 经测试的字线段（12）。
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