公开(公告)号：US20220178979A1

公开(公告)日：2022-06-09

申请号：US17115359

申请日：2020-12-08

申请人： Cree, Inc.

发明人： James Richmond ,  Edward Robert Van Brunt

IPC分类号： G01R27/02 ,  H01L29/16 ,  H01L29/78

摘要： Semiconductor devices, and in particular semiconductor devices for improved resistance measurements and related methods are disclosed. Contact structures for semiconductor devices are disclosed that provide access to resistance measurements with reduced influence of testing-related resistances, thereby improving testing accuracy, particularly for semiconductor devices with low on-resistance ratings. A semiconductor device may include an active region and an inactive region that is arranged along a perimeter of the active region. The semiconductor device may be arranged with a topside contact to provide access for resistance measurements, for example Kelvin-sensing resistance measurements. Related methods include performing resistance measurements from a topside of the semiconductor device, even when the active region of the semiconductor device forms a vertical contact structure.

公开(公告)号：US20220140138A1

公开(公告)日：2022-05-05

申请号：US17087740

申请日：2020-11-03

申请人： Cree, Inc.

发明人： Edward Robert Van Brunt ,  Sei-Hyung Ryu

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/423

摘要： Semiconductor devices, and in particular protection structures for semiconductor devices that include sensor arrangements are disclosed. A semiconductor device may include a sensor region, for example a current sensor region that occupies a portion of an overall active area of the device. The current sensor region may be configured to provide monitoring of device load currents during operation. Semiconductor devices according to the present disclosure include one or more protection structures that are configured to allow the semiconductor devices to withstand transient voltage events without device failure. A protection structure may include an insulating layer that is provided in a transition region between a device region and the sensor region of the semiconductor device. In the example of an insulated gate semiconductor device, the insulating layer of the protection structure may include a material with a greater breakdown voltage than a breakdown voltage of a gate insulating layer.

公开(公告)号：US20210343847A1

公开(公告)日：2021-11-04

申请号：US16863642

申请日：2020-04-30

申请人： Cree, Inc.

发明人： Daniel Jenner Lichtenwalner ,  Edward Robert Van Brunt

IPC分类号： H01L29/423 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78

摘要： Power switching devices include a semiconductor layer structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells and the inactive region comprising a gate pad on the semiconductor layer structure and a gate bond pad on and electrically connected to the gate pad, an isolation layer between the gate pad and the gate bond pad, and a barrier layer between the gate pad and the isolation layer.

公开(公告)号：US11075264B2

公开(公告)日：2021-07-27

申请号：US15168310

申请日：2016-05-31

申请人： Cree, Inc.

发明人： Edward Robert Van Brunt ,  Alexander V. Suvorov ,  Vipindas Pala ,  Daniel J. Lichtenwalner ,  Qingchun Zhang

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/66 ,  H01L29/872 ,  H01L21/04 ,  H01L29/78 ,  H01L29/10

摘要： Semiconductor devices include a silicon carbide drift region having an upper portion and a lower portion. A first contact is on the upper portion of the drift region and a second contact is on the lower portion of the drift region. The drift region includes a superjunction structure that includes a p-n junction that is formed at an angle of between 10° and 30° from a plane that is normal to a top surface of the drift region. The p-n junction extends within +/−1.5° of a crystallographic axis of the silicon carbide material forming the drift region.

公开(公告)号：US10103230B2

公开(公告)日：2018-10-16

申请号：US15339178

申请日：2016-10-31

申请人： Cree, Inc.

发明人： Edward Robert Van Brunt ,  Alexander V. Suvorov ,  Vipindas Pala ,  Lin Cheng

IPC分类号： H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L21/324 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L21/04 ,  H01L29/872 ,  H01L29/861 ,  H01L21/265

摘要： A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron.

公开(公告)号：US20150263145A1

公开(公告)日：2015-09-17

申请号：US14212991

申请日：2014-03-14

申请人： Cree, Inc.

发明人： Vipindas Pala ,  Edward Robert Van Brunt ,  Lin Cheng

IPC分类号： H01L29/739 ,  H01L29/16 ,  H01L29/66

摘要： An IGBT device includes an IGBT stack, a collector contact, a gate contact, and an emitter contact. The IGBT stack includes an injector region, a drift region over the injector region, a spreading region over the drift region, and a pair of junction implants in the spreading region. The spreading region provides a first surface of the IGBT stack, which is opposite the drift region. The pair of junction implants is separated by a channel, and extends from the first surface of the IGBT stack along a lateral edge of the IGBT stack towards the drift region to a first depth, such that the thickness of the spreading region is at least one and a half times greater than the first depth.

摘要翻译： IGBT器件包括IGBT堆叠，集电极触点，栅极触点和发射极触点。 IGBT堆叠包括喷射器区域，喷射器区域上方的漂移区域，漂移区域上的扩展区域以及扩展区域中的一对结植入物。 扩展区域提供与漂移区域相对的IGBT堆叠的第一表面。 一对结植入物被沟道隔开，并且沿着IGBT堆叠的横向边缘朝向漂移区从第一表面延伸到第一深度，使得扩展区的厚度为至少一个 比第一深度大半倍。

公开(公告)号：US20150084118A1

公开(公告)日：2015-03-26

申请号：US14032919

申请日：2013-09-20

申请人： Cree, Inc.

发明人： Edward Robert Van Brunt ,  Vipindas Pala ,  Lin Cheng

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7806 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66712

摘要： A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the source contact are separated from the drain contact by at least a drift layer. The Schottky bypass diode is coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed throughout the drift layer by the Schottky bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact within the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction.

摘要翻译： 半导体器件包括垂直FET器件和肖特基旁路二极管。 垂直FET器件包括栅极接触，源极接触和漏极接触。 至少一个漂移层将栅极接触和源极接触与漏极接触部分离开。 肖特基旁路二极管耦合在源触点和漏极触点之间，并且与垂直FET器件相邻地单片集成，使得放置在源极触点和漏极触点之间的电压通过肖特基旁路二极管分布在整个漂移层中 防止形成在垂直FET器件内的源极触点和漏极接触之间的多个PN结中的每一个上的电压超过相应PN结的势垒电压的方式。

公开(公告)号：US20150084062A1

公开(公告)日：2015-03-26

申请号：US14255405

申请日：2014-04-17

申请人： Cree, Inc.

发明人： Vipindas Pala ,  Lin Cheng ,  Anant Kumar Agarwal ,  John Williams Palmour ,  Edward Robert Van Brunt

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC分类号： H01L29/7806 ,  H01L21/046 ,  H01L21/26506 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/782 ,  H01L29/7828 ,  H01L29/8611 ,  H01L29/872

摘要： A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.

公开(公告)号：US20150028351A1

公开(公告)日：2015-01-29

申请号：US14297074

申请日：2014-06-05

申请人： Cree, Inc.

发明人： Edward Robert Van Brunt ,  Alexander V. Suvorov ,  Vipindas Pala ,  Lin Cheng

IPC分类号： H01L29/16 ,  H01L29/66

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L21/047 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0619 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron.

摘要翻译： 根据一些实施例的半导体器件结构包括具有第一导电类型的碳化硅衬底，在碳化硅衬底上具有第一导电类型的碳化硅漂移层，并且具有与碳化硅衬底相对的上表面，以及掩埋结结构 在碳化硅漂移层中。 掩埋结结构具有与第一导电类型相反的第二导电类型，并且具有大于约一微米的结深度。

公开(公告)号：US20220093791A1

公开(公告)日：2022-03-24

申请号：US17031365

申请日：2020-09-24

申请人： Cree, Inc.

发明人： Edward Robert Van Brunt ,  Thomas E. Harrington, III

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/16

摘要： Semiconductor devices, and more particularly semiconductor devices with improved edge termination structures are disclosed. A semiconductor device includes a drift region that forms part of an active region. An edge termination region is arranged along a perimeter of the active region and also includes a portion of the drift region. The edge termination region includes one or more sub-regions of an opposite doping type than the drift region and one or more electrodes may be capacitively coupled to the drift region by way of the one or more sub-regions. During a forward blocking mode for the semiconductor device, the one or more electrodes may provide a path that draws ions away from passivation layers that are on the edge termination region and away from the active region. In this manner, the semiconductor device may exhibit reduced leakage, particularly at higher operating voltages and higher associated operating temperatures.