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公开(公告)号：US11094848B2
公开(公告)日：2021-08-17
申请号：US16542458
申请日：2019-08-16
Applicant: Cree, Inc.
Inventor： Luis Breva , Colin Stuart , Michael Check
Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders.
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公开(公告)号：US20200176507A1
公开(公告)日：2020-06-04
申请号：US16203709
申请日：2018-11-29
Applicant: Cree, Inc.
Inventor： Nikolas Hall , Derek Miller , Anoop Mathew , Colin Blakely , Luis Breva , Jesse Reiherzer , David Todd Emerson
Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips and related methods are disclosed. LED chips are provided that include an indicia arranged between a primary light-emitting face and a mounting face of the LED chip. The indicia may include at least one of a logo, one or more alphanumeric characters, or a symbol, among others that are configured to convey information. Arrangements of at least one of an n-contact, a p-contact, or a reflector layer of the LED chip may form the indicia. LED chips are also provided where at least a portion of an indicia is arranged on a mounting face of the LED chip. Indicia are provided that may be visible through primary light-emitting faces when LED chips are electrically activated or electrically deactivated. In this regard, the indicia may be embedded within LED chips while still being able to convey information.
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公开(公告)号：US11145689B2
公开(公告)日：2021-10-12
申请号：US16203709
申请日：2018-11-29
Applicant: Cree, Inc.
Inventor： Nikolas Hall , Derek Miller , Anoop Mathew , Colin Blakely , Luis Breva , Jesse Reiherzer , David Todd Emerson
Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips and related methods are disclosed. LED chips are provided that include an indicia arranged between a primary light-emitting face and a mounting face of the LED chip. The indicia may include at least one of a logo, one or more alphanumeric characters, or a symbol, among others that are configured to convey information. Arrangements of at least one of an n-contact, a p-contact, or a reflector layer of the LED chip may form the indicia. LED chips are also provided where at least a portion of an indicia is arranged on a mounting face of the LED chip. Indicia are provided that may be visible through primary light-emitting faces when LED chips are electrically activated or electrically deactivated. In this regard, the indicia may be embedded within LED chips while still being able to convey information.
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公开(公告)号：US20210050482A1
公开(公告)日：2021-02-18
申请号：US16542458
申请日：2019-08-16
Applicant: Cree, Inc.
Inventor： Luis Breva , Colin Stuart , Michael Check
Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders.
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