公开(公告)号：US20210050485A1

公开(公告)日：2021-02-18

申请号：US16963533

申请日：2019-01-28

Applicant: Cree, Inc.

Inventor： Michael Check ,  Kevin Haberern

IPC: H01L33/46

Abstract: A light-emitting diode (LED) chip with reflective layers having high reflectivity is disclosed. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer. An adhesion layer may be provided between the first reflective layer and the second reflective layer. The adhesion layer may comprise a metal oxide that promotes improved adhesion with reduced optical losses.

公开(公告)号：US20210336093A1

公开(公告)日：2021-10-28

申请号：US16857721

申请日：2020-04-24

Applicant: Cree, Inc.

Inventor： Daniel E. Stasiw ,  Steven Wuester ,  Michael Check

IPC: H01L33/48 ,  H01L33/60 ,  H01L33/62 ,  H01L25/075 ,  H01L33/00

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures with electrical overstress protection are disclosed. LED chip structures are disclosed that include built-in electrical overstress protection. An exemplary LED chip may include an active LED structure that is arranged as a primary light-emitting structure and a separate active LED structure that is arranged as an electrical overstress protection structure. The electrical overstress protection structure may be electrically connected in reverse relative to the primary light-emitting structure. In this manner, under normal operating conditions, forward current will flow through the primary light-emitting structure to generate desired light emissions, and during an electrical overstress event, reverse current may flow through the electrical overstress protection structure, thereby protecting the light-emitting structure from damage.

公开(公告)号：US11031527B2

公开(公告)日：2021-06-08

申请号：US15882103

申请日：2018-01-29

Applicant: Cree, Inc.

Inventor： Michael Check

IPC: H01L33/46 ,  H01L33/38 ,  H01L33/42 ,  H01L33/32 ,  H01L33/44 ,  H01L33/60 ,  H01L33/14 ,  H01L33/22 ,  H01L33/08

Abstract: A light-emitting diode (LED) chip with reflective layers having high reflectivity. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer.

公开(公告)号：US20210050482A1

公开(公告)日：2021-02-18

申请号：US16542458

申请日：2019-08-16

Applicant: Cree, Inc.

Inventor： Luis Breva ,  Colin Stuart ,  Michael Check

IPC: H01L33/38 ,  H01L33/46 ,  H01L33/62 ,  H01L33/40

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders.

公开(公告)号：US10804452B2

公开(公告)日：2020-10-13

申请号：US16222173

申请日：2018-12-17

Applicant: Cree, Inc.

Inventor： Michael Check

IPC: H01L33/62 ,  H01L23/00 ,  H01L33/00 ,  H01L33/46 ,  H01L33/60

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chips with interconnect structures are disclosed. LED chips are provided that include first interconnects electrically coupled to an n-type layer and second interconnects electrically connected to a p-type layer. Configurations of the first and second interconnects are provided that may improve current spreading by reducing localized areas of current crowding within LED chips. Various configurations are disclosed that include collectively formed symmetric patterns of the first and second interconnects, diameters of certain ones of either the first or second interconnects that vary based on their relative positions in LED chips, and spacings of the second interconnects that vary based on their distances from the first interconnects. In this regard, LED chips are disclosed with improved current spreading as well as higher lumen outputs and efficiencies.

公开(公告)号：US20190237630A1

公开(公告)日：2019-08-01

申请号：US15882103

申请日：2018-01-29

Applicant: Cree, Inc.

Inventor： Michael Check

IPC: H01L33/46 ,  H01L33/42 ,  H01L33/38

CPC classification number: H01L33/46 ,  H01L33/08 ,  H01L33/14 ,  H01L33/22 ,  H01L33/32 ,  H01L33/382 ,  H01L33/42 ,  H01L33/44 ,  H01L33/60

Abstract: A light-emitting diode (LED) chip with reflective layers having high reflectivity. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer.

公开(公告)号：US11094848B2

公开(公告)日：2021-08-17

申请号：US16542458

申请日：2019-08-16

Applicant: Cree, Inc.

Inventor： Luis Breva ,  Colin Stuart ,  Michael Check

IPC: H01L33/38 ,  H01L33/40 ,  H01L33/46 ,  H01L33/62 ,  H01L33/22 ,  H01L33/32

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders.